EP9307 Datasheet, PDF (44/48 Pages) Cirrus Logic – ARM9 SOC WITH ETHERNET USB DISPLAY AND TOUCHSCREEN

EP9307
ARM9 SOC with Ethernet, USB, Display and Touchscreen
The following section focuses on the EP9307 pin signals
from two viewpoints - the pin usage and pad
characteristics, and the pin multiplexing usage. The first
table (Table S) is a summary of all the EP9307 pin
signals. The second table (Table T) illustrates the pin
signal multiplexing and configuration options.
Table S is a summary of the EP9307 pin signals, which
illustrates the pad type and pad pull type (if any). The
symbols used in the table are defined as follows. (Note: A
blank box means Not Applicable (NA) or, for Pull Type,
No Pull (NP).)
Under the Pad Type column:
• A - Analog pad
• P - Power pad
• G - Ground pad
• I - Pin is an input only
• I/O - Pin is input/output
• 4mA - Pin is a 4mA output driver
• 8mA - Pin is an 8mA output driver
• 12mA - Pin is an 12mA output driver
See the text description for additional information about
bi-directional pins.
Under the Pull Type Column:
• PU - Resistor is a pull up to the RVDD supply
• PD - Resistor is a pull down to the RGND supply
.
Table S. Pin Descriptions
Pin Name
TCK
TDI
TDO
TMS
TRSTn
BOOT[1:0]
XTALI
XTALO
VDD_PLL
GND_PLL
RTCXTALI
RTCXTALO
WRn
RDn
WAITn
AD[25:0]
DA[31:0]
CSn[3:0]
CSn[7:6]
DQMn[3:0]
SDCLK
SDCLKEN
SDCSn[3:0]
RASn
CASn
SDWEn
P[17:0]
SPCLK
HSYNC
Block
JTAG
JTAG
JTAG
JTAG
JTAG
System
PLL
PLL
PLL
PLL
RTC
RTC
EBUS
EBUS
EBUS
EBUS
EBUS
EBUS
EBUS
EBUS
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
Raster
Raster
Raster
Pad Pull
Type Type
Description
I
I
4ma
I
I
I
A
A
P
G
A
A
4ma
4ma
I
8ma
8ma
4ma
4ma
8ma
8ma
8ma
4ma
8ma
8ma
8ma
4ma
12ma
8ma
PD JTAG clock in
PD JTAG data in
- JTAG data out
PD JTAG test mode select
PD JTAG reset
PD Boot mode select in
- Main oscillator input
- Main oscillator output
- Main oscillator power, 1.8V
- Main oscillator ground
- RTC oscillator input
- RTC oscillator output
- SRAM Write strobe out
- SRAM Read/OE strobe out
PU SRAM Wait in
- Shared Address bus out
PU Shared Data bus in/out
PU Chip select out
PU Chip select out
- Shared data mask out
- SDRAM clock out
- SDRAM clock enable out
- SDRAM chip selects out
- SDRAM RAS out
- SDRAM CAS out
- SDRAM write enable out
PU Pixel data bus out
PU Pixel clock in/out
PU Horizontal synchronization/ line pulse out
Table S. Pin Descriptions (Continued)
Pin Name
V_CSYNC
BLANK
BRIGHT
PWMOUT
Xp, Xm
Yp, Ym
sXp, sXm
sYp, sYm
VDD_ADC
GND_ADC
COL[7:0]
ROW[7:0]
USBp[2:0]
USBm[2:0]
TXD0
RXD0
CTSn
DSRn
DTRn
RTSn
TXD1
RXD1
TXD2
RXD2
MDC
MDIO
RXCLK
MIIRXD[3:0]
RXDVAL
Block
Raster
Raster
Raster
PWM
ADC
ADC
ADC
ADC
ADC
ADC
Key
Key
USB
USB
UART1
UART1
UART1
UART1
UART1
UART1
UART2
UART2
UART3
UART3
EMAC
EMAC
EMAC
EMAC
EMAC
Pad Pull
Type Type
Description
8ma
PU
Vertical or composite synchronization/frame
pulse out
8ma PU Composite blanking signal out
4ma
- PWM brightness control out
8ma
Pulse width modulator output
A
- Touchscreen ADC X axis
A
- Touchscreen ADC Y axis
A
- Touchscreen ADC X axis feedback
A
- Touchscreen ADC Y axis feedback
P
- Touchscreen ADC power, 3.3V
G
- Touchscreen ADC ground
8ma PU Key matrix column inputs
8ma PU Key matrix row outputs
A
- USB positive signals
A
- USB negative signals
4ma
- Transmit out
I
PU Receive in
I
PU Clear to send/transmit enable
I
PU Data set ready/Data Carrier Detect
4ma
- Data Terminal Ready output
4ma
- Ready to send
4ma
- Transmit/IrDA output
I
PU Receive/IrDA input
4ma
- Transmit
I
PU Receive
4ma
Management data clock
4ma PU Management data input/output
I
PD Receive clock in
I
PD Receive data in
I
PD Receive data valid
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