CDB61581 Datasheet, PDF (4/16 Pages) Cirrus Logic – Universal Line Interface Unit

CDB61581
3. TRANSMIT CIRCUIT
The transmit clock and data signals are supplied on
BNC inputs labeled TCLK, TPOS, and TNEG. In
Hardware and Host mode (with coder mode dis-
abled), data is supplied on the TPOS and TNEG
BNC inputs. In Host mode with coder mode en-
abled, data is supplied on the TDATA BNC input.
The transmitter output is transformer coupled to the
line through the step-up transformer T2. The signal
is available at either the Transmit binding posts
(J11, J13) or the Transmit bantam jack. Capacitor
C12 prevents output stage imbalances from pro-
ducing a DC current that may saturate the trans-
former, thus degrading its performance.
4. RECEIVE CIRCUIT
The receive signal is input at either the Receive
binding posts (J4, J10) or the Receive bantam jack.
The receive signal is transformer coupled to the
CS61581 through 1:1 transformer T1.
The receive line is terminated by resistors R1-R2 to
provide impedance matching and receiver return
loss. They are socketed so the values may be
changed according to the application. The evalua-
tion board is supplied from the factory with 50 Ω
resistors for terminating 100 Ω twisted-pair T1
lines, 60 Ω resistors for terminating 120 Ω twisted-
pair E1 lines, and 37.5 Ω resistors for terminating
75 Ω coaxial E1 lines. Capacitor C3 provides an
AC ground reference for the differential input.
The recovered clock and data signals are available
on BNC outputs labeled RCLK, RPOS, and RNEG.
In Hardware and Host mode (with coder mode dis-
abled), data is available on the RPOS and RNEG
BNC. With coder mode enabled, data is available
on the RDATA BNC output in unipolar format and
bipolar violations are reported on the RNEG BNC
connector.
5. REFERENCE CLOCK
The CDB61581 requires a T1 or E1 reference clock
for operation. This clock can be supplied by either
a quartz crystal or an external reference. The eval-
uation board is supplied from the factory with two
quartz crystals for T1 and E1 operations, respec-
tively. In the case that both the external reference
and the quartz crystal are applied, the external ref-
erence takes precedence.
5.1. Quartz Crystal
A quartz crystal may be inserted at socket Y1. The
quartz crystals operate at 4X the frequency of oper-
ation i.e. the T1 quartz crystal runs at 6.176 MHz
and the E1 quartz crystal at 8.192 MHz.
5.2. External Reference
An external reference of 1.544 MHz or 2.048 MHz
may be provided at the REFCLK BNC input for T1
or E1 applications, respectively. Header HDR7
must be jumpered in the "MCLK" position to pro-
vide connectivity to the MCLK pin of the
CS61581.
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DS211DB2