CS42518 Datasheet, PDF(37/91 Page) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

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CS42518 Datasheet, PDF (37/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

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CS42518

4.6.4e OLM Config #5

This One-Line Mode configuration can support up to 8 channels of DAC data, 2 channels of ADC data

and 2 channels of S/PDIF received data and will handle up to 24-bit samples at a sampling frequency of

48 kHz on all channels for both the DAC and ADC. The output data stream of the internal ADCs can be

configured to use the CX_SDOUT output and run at the CODEC_SP clock speeds or to use the

SAI_SDOUT data output and run at the SAI_SP rate. The CODEC_SP and SAI_SP can operate at differ-

ent Fs rates.

Functional Mode Register (addr = 03h)

Set CODEC_FMx = 00,01,10

Set SAI_FMx = 00,01,10

Set ADC_SP SELx = 00,01,10

Interface Format Register (addr = 04h)

Set DIFx bits to proper serial format

Set ADC_OLx bits = 00

Set DAC_OLx bits = 00,01

Misc. Control Register (addr = 05h)

Set CODEC_SP M/S = 0 or 1

Set SAI_SP M/S = 0 or 1

Set EXT ADC SCLK = 0

Description

CX_LRCK can run at SSM, DSM, or QSM independent of SAI_LRCK

SAI_LRCK can run at SSM, DSM, or QSM independent of CX_LRCK

Configure ADC data to use CX_SDOUT and CODEC_SP clocks, or

SAI_SDOUT and SAI_SP cocks.

Select the digital interface format when not in one line mode

Set ADC operating mode to Not One Line Mode since only 2 channels of

ADC are supported

Select DAC operating mode, see table below for valid combinations

Set CODEC Serial Port to master mode or slave mode.

Set Serial Audio Interface Port to master mode or slave mode.

External ADCs are not used. Leave bit in default state.

CX_SDOUT= ADC Data

SAI_SDOUT=ADC or

S/PDIF Data

ADC Mode

Not One

Line Mode

One Line

Mode #1

One Line

Mode #2

Not One Line Mode

CX_SCLK=64 Fs

CX_LRCK=SSM/DSM/QSM

SAI_SCLK=64 Fs

SAI_LRCK=SSM/DSM/QSM

not valid

DAC Mode

One Line Mode #1

CX_SCLK=128 Fs

CX_LRCK=SSM/DSM

SAI_SCLK=64 Fs

SAI_LRCK=SSM/DSM/QSM

not valid

One Line Mode #2

not valid

RMCK

ADCIN1

ADCIN2

MCLK

SAI_SCLK

SAI_LRCK

SAI_SDOUT

CX_SCLK

CX_LRCK

CX_SDOUT

64Fs,128Fs, 256Fs

SPDIF or ADC Data

64Fs,128Fs, 256Fs

ADC Data

SCLK_PORT1

LRCK_PORT1

SDIN_PORT1

SCLK_PORT2

LRCK_PORT2

SDIN_PORT2

CX_SDIN1

CX_SDIN2

CX_SDIN3

CX_SDIN4

CS42518

SCLK_PORT3

LRCK_PORT3

SDOUT1_PORT3

SDOUT2_PORT3

SDOUT3_PORT3

SDOUT4_PORT3

DIGITAL AUDIO

PROCESSOR

Figure 20. OLM Configuration #5

DS584PP5

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