CS42518 Datasheet, PDF (14/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

CS42518
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI^TM FORMAT
(For CQZ, T_A = -10 to +70° C; For DQZ, T_A = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to
5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol Min Typ Max Units
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 19)
f_sck
0
-
6.0
MHz
t_csh
1.0
-
-
µs
t_css
20
-
-
ns
t_scl
66
-
-
ns
t_sch
66
-
-
ns
t_dsu
40
-
-
ns
(Note 20)
t_dh
15
-
-
ns
t_pd
-
-
50
ns
t_r1
-
-
25
ns
t_f1
-
-
25
ns
(Note 21)
t_r2
-
-
100
ns
(Note 21)
t_f2
-
-
100
ns
Notes: 19. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For f_sck <1 MHz.
CS
t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
CDOUT
t _dsu
t _dh
t _pd
Figure 4. Control Port Timing - SPI Format
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DS584PP5