CS42518 Datasheet, PDF(26/91 Page) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

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CS42518 Datasheet, PDF (26/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

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CS42518

4.5.2 OMCK System Clock Mode

A special clock switching mode is available that allows the clock that is input through the OMCK pin to be

used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register âClock Con-

trol (address 06h)â on page 53. An advanced auto switching mode is also implemented to maintain master

clock functionality. The clock auto switching mode allows the clock input through OMCK to be used as a

clock in the system without any disruption when the PLL loses lock; for example, when the input is re-

moved from the receiver. This clock switching is done glitch free. A clock adhering to the specifications

detailed in the Switching Characteristics table on page 12 must be applied to the OMCK pin at all times

that the FRC_PLL_LK bit is set to â0â (See âForce PLL Lock (FRC_PLL_LK)â on page 54).

Sample

OMCK (MHz)

Rate

Single Speed

Double Speed

Quad Speed

(kHz)

(4 to 50 kHz)

(50 to 100 kHz)

(100 to 192 kHz)

256x 384x 512x 128x 192x 256x 64x

96x 128x

48 12.2880 18.4320 24.5760 -

- 12.2880 18.4320 24.5760 -

192

- 12.2880 18.4320 24.5760

Table 1. Common OMCK Clock Frequencies

4.5.3 Master Mode

In master mode, the serial interface timings are derived from an external clock attached to OMCK or the

output of the PLL with an input reference to either the S/PDIF Receiver recovered clock or the SAI_LRCK

input from the Serial Audio Interface Port. Master clock selection and operation is configured with the

SW_CTRL1:0 bits in the Clock Control Register (See âClock Control (address 06h)â on page 53).

The supported PLL output frequencies are shown in Table 2 below.

Sample

Rate

(kHz)

44.1

88.2

176.4

192

Single Speed

(4 to 50 kHz)

256x

8.1920

11.2896

12.2880

PLL Output (MHz)

Double Speed

(50 to 100 kHz)

256x

16.3840

22.5792

24.5760

Quad Speed

(100 to 192 kHz)

256x

45.1584

49.1520

Table 2. Common PLL Output Clock Frequencies

4.5.4 Slave Mode

In Slave mode, CX_LRCK, CX_SCLK and/or SAI_LRCK, SAI_SCLK operate as inputs. The Left/Right

clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the supplied

master clock, OMCK or the output of the PLL. The serial bit clock, CX_SCLK and/or SAI_SCLK, must be

synchronously derived from the master clock and be equal to 128x, 64x, 48x or 32x Fs depending on the

interface format selected and desired speed mode. One Line Mode #1 is supported in Slave Mode. One

Line Mode #2 is not supported. Refer to Table 3 for required clock ratios. The sample rate to OMCK ratios

and OMCK frequency requirements for Slave mode operation are shown in Table 1.

OMCK/LRCK Ratio

Single Speed

Double Speed

256x, 384x, 512x 128x, 192x, 256x

Quad Speed

64x, 96x, 128x

One Line Mode #1

256x

Table 3. Slave Mode Clock Ratios

DS584PP5

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