CS42435 Datasheet, PDF (36/58 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out TDM CODEC

CS42435
SCL
SDA
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CHIP ADDRESS (WRITE)
MAP BYTE
STOP
CHIP ADDRESS (READ)
DATA
DATA +1 DATA + n
1 0 0 1 0 AD1 AD0 0
INCR 6 5 4 3 2 1 0
1 0 0 1 0 AD1 AD0 1
70
7
0
7
0
START
ACK
ACK
START
ACK
ACK
NO
ACK _STOP
Figure 18. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 18, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10010xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10010xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
5.8 Recommended Power-Up Sequence
5.8.1
Hardware Mode
1. Hold RST low until the power supply, clocks and hardware control pins are stable. In this state, the
control port is reset to its default settings and VQ will remain low.
2. Bring RST high. The device will initially be in a low power state with VQ low.
3. The device will initiate the Hardware Mode power up sequence. All features will default to the
Hardware Mode defaults as listed in Table 2 on page 27 according to the Hardware Mode control
pins. VQ will quick-charge to approximately VA/2 and the analog output bias will clamp to VQ.
4. Following approximately 2000 sample periods, the device is initialized and ready for normal operation.
Note: During the Hardware Mode power-up sequence, there must be no transitions on any of the hard-
ware control pins.
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