CS42435 Datasheet, PDF (28/58 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out TDM CODEC

CS42435
Function
DAC Auto-Mute
Status Interrupt
Hardware Mode Feature Summary
Default Configuration
Hardware Control
Enabled
-
-
N/A
-
-
Table 2. Hardware Configurable Settings (Continued)
Note
5.2 Analog Inputs
5.2.1
Line-Level Inputs
AINx+ and AINx- are the line-level differential analog inputs internally biased to VQ, approximately VA/2.
Figure 9 on page 28 shows the full-scale analog input levels. The CS42435 also accommodates single-
ended signals on all inputs, AIN1-AIN4. See “ADC Input Filter” on page 49 for the recommended input
filters.
5.2.1.1 Hardware Mode
AIN Volume Control and ADC Overflow status are not accessible in Hardware Mode.
5.2.1.2 Software Mode
For single-ended operation on ADC1-ADC2 (AIN1 to AIN4), the ADCx_SINGLE bit in the register “ADC
Control & DAC De-Emphasis (Address 05h)” on page 43 must be set appropriately (see Figure 20 on
page 49 for required external components).
The gain/attenuation of the signal can be adjusted for each AINx independently through the “AINX Volume
Control (Address 11h-14h)” on page 46. The ADC output data is in 2’s complement binary format. For in-
puts above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, re-
spectively, and cause the ADC Overflow bit in the register “Status (Address 19h) (Read Only)” on page 47
to be set to a ‘1’.
5.0 V
3.9 V
2.5 V
1.1 V
3.9 V
2.5 V
1.1 V
VA
AINx+
AINx-
Full-Scale Differential Input Level =
(AINx+) - (AINx-) = 5.6 VPP = 1.98 VRMS
Figure 9. Full-Scale Input
5.2.2
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is disabled during normal operation, the current value of the DC offset for the
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