CS42435 Datasheet, PDF (3/58 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 8-Out TDM CODEC

CS42435
5.9 Reset and Power-Up ...................................................................................................................... 37
5.10 Power Supply, Grounding, and PCB Layout ................................................................................. 37
6. REGISTER QUICK REFERENCE ......................................................................................................... 38
7. REGISTER DESCRIPTION ................................................................................................................... 40
7.1 Memory Address Pointer (MAP) ..................................................................................................... 40
7.1.1 Increment (INCR) .................................................................................................................. 40
7.1.2 Memory Address Pointer (MAP[6:0]) ..................................................................................... 40
7.2 Chip I.D. and Revision Register (Address 01h) (Read Only) .......................................................... 40
7.2.1 Chip I.D. (CHIP_ID[3:0]) ........................................................................................................ 40
7.2.2 Chip Revision (REV_ID[3:0]) ................................................................................................. 40
7.3 Power Control (Address 02h) ......................................................................................................... 41
7.3.1 Power Down ADC Pairs (PDN_ADCX) ................................................................................. 41
7.3.2 Power Down DAC Pairs (PDN_DACX) ................................................................................. 41
7.3.3 Power Down (PDN) ............................................................................................................... 41
7.4 Functional Mode (Address 03h) ...................................................................................................... 42
7.4.1 MCLK Frequency (MFREQ[2:0]) ........................................................................................... 42
7.5 Miscellaneous Control (Address 04h) ............................................................................................. 42
7.5.1 Freeze Controls (FREEZE) ................................................................................................... 42
7.5.2 Auxiliary Digital Interface Format (AUX_DIF) ........................................................................ 42
7.6 ADC Control & DAC De-Emphasis (Address 05h) ......................................................................... 43
7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) .................................................. 43
7.6.2 DAC De-Emphasis Control (DAC_DEM) ............................................................................... 43
7.6.3 ADC1 Single-Ended Mode (ADC1 SINGLE) ......................................................................... 43
7.6.4 ADC2 Single-Ended Mode (ADC2 SINGLE) ......................................................................... 44
7.7 Transition Control (Address 06h) .................................................................................................... 44
7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) .................................................... 44
7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) .................................. 44
7.7.3 Auto-Mute (AMUTE) .............................................................................................................. 45
7.7.4 Mute ADC Serial Port (MUTE ADC_SP) ............................................................................... 45
7.8 DAC Channel Mute (Address 07h) ................................................................................................. 45
7.8.1 Independent Channel Mute (AOUTX_MUTE) ....................................................................... 45
7.9 AOUTX Volume Control (Addresses 08h- 0Fh) .......................................................................... 46
7.9.1 Volume Control (AOUTX_VOL[7:0]) ...................................................................................... 46
7.10 DAC Channel Invert (Address 10h) .............................................................................................. 46
7.10.1 Invert Signal Polarity (INV_AOUTX) .................................................................................... 46
7.11 AINX Volume Control (Address 11h-14h) ..................................................................................... 46
7.11.1 AINX Volume Control (AINX_VOL[7:0]) .............................................................................. 46
7.12 ADC Channel Invert (Address 17h) .............................................................................................. 47
7.12.1 Invert Signal Polarity (INV_AINX) ........................................................................................ 47
7.13 Status (Address 19h) (Read Only) ................................................................................................ 47
7.13.1 CLOCK ERROR (CLK ERROR) .......................................................................................... 47
7.13.2 ADC Overflow (ADCX_OVFL) ............................................................................................. 47
7.14 Status Mask (Address 1Ah) .......................................................................................................... 48
8. EXTERNAL FILTERS............................................................................................................................ 49
8.1 ADC Input Filter .............................................................................................................................. 49
8.1.1 Passive Input Filter ................................................................................................................ 50
8.1.2 Passive Input Filter w/Attenuation ......................................................................................... 50
8.2 DAC Output Filter ........................................................................................................................... 51
9. ADC FILTER PLOTS............................................................................................................................. 52
10. DAC FILTER PLOTS........................................................................................................................... 54
11. PARAMETER DEFINITIONS............................................................................................................... 56
12. REFERENCES..................................................................................................................................... 56
13. PACKAGE INFORMATION................................................................................................................. 57
13.1 Thermal Characteristics ............................................................................................................... 57
DS685F1
3