CS4218 Datasheet, PDF (34/44 Pages) Cirrus Logic – 16-Bit Stereo Audio Codec

CS4218
Miscellaneous
RESET - Reset Input, PIN 2.(L), 40(Q).
Resets the CS4218 to a known state, and must be initiated after power-up or power-down
mode. Releasing RESET causes the CS4218 to initiate a calibration sequence. The CS4218
automatically initiates a calibration sequence after a sample rate change in master and slave
modes.
CLKIN - Master Clock, PIN 3(L), 41(Q).
CLKIN is the master clock that operates the internal logic. CLKIN is 256×Fs_max, where Fs_max
is the highest sample frequency needed, for SM3 Master and Slave, and for SM4 Master and
Slave. CLKIN is 16xFs_max in SM3 Multiplier sub-modes. Different sample frequencies are
obtained by either changing the ratio of SCLK to CLKIN in slave modes, or changing the
format pin values (F2-F0) in master modes.
PDN - Power Down, PIN 13(L), 7(Q).
This pin, when low, causes the CS4218 to go into a power down state. RESET should be held
low for 50 ms when exiting the power down state to allow time for the voltage reference to
settle.
DI1 - Parallel Digital Bit Input #1, PIN 33(L), 27(Q).
This pin value is reflected in the DI1 bit in the sub-frame.
DO1 - Parallel Digital Bit Output #1, PIN 37(L), 31(Q).
This pin reflects the value of the DO1 bit in the sub-frame
FILT - PLL Filter, PIN 6(L), 44(Q).
This pin should have the 0.47 µF PLL loop filter capicator connected when using SM3
Multiplier sub-modes. When using SM3-M, SM3-S, SM4, or SM5 modes, this pin should be
left floating. This pin has an internal pull-down making the CS4218 pin compatible with the
CS4216 operating in serial modes SM3-M, SM3-S, and SM4.
NC - No Connection,
PINS 7, 8, 9, 10, 11, 12, 14, 17, 18, 19(L)
PINS 1, 2, 3, 4, 5, 6, 8, 11, 12, 13(Q).
These pins should be left floating with no trace attached to allow backwards compatibility with
future revisions. They should not be used as a convenient path for signal traces.
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DS135F1