CS4218 Datasheet, PDF (20/44 Pages) Cirrus Logic – 16-Bit Stereo Audio Codec

CS4218
Slave Sub-Mode (SM3-S)
In SM3, Slave sub-mode is selected by setting
MF4:MA = 0 which configures SSYNC and
SCLK as inputs to the CS4218. These two sig-
nals must be externally derived from CLKIN. In
SM3-S and SM3-MS sub-modes, the phase rela-
tionship between SCLK/SSYNC and CLKIN
cannot be controlled since SCLK and SSYNC
are externally derived. Therefore, the noise per-
formance may be slightly worse than when using
the master sub-modes.
The number of sub-frames on the serial port is
selected using MF1:F1 and MF2:F2. In SM3-S
and SM3-MS sub-modes, MF3:F3 works as an
additional general purpose input DI3. Figures 16
through 18 illustrate the SM3-S and SM3-MS
sub-mode formats.
Bits per Frame (Slave Sub-Modes)
In slave sub-modes, MF1:F1 and MF2:F2 select
the number of bits per frame, which determines
how many CS4218s can occupy one serial port.
Table 4 lists the decoding for MF1:F1 and
MF2:F2.
When set for 64 SCLKs per frame, one device
occupies the entire frame; therefore, a sub-frame
is equivalent to a frame. MF7:SFS1 and
MF8:SFS2 must be set to zero.
When set for 128 SCLKs per frame, two devices
can occupy the serial port, with MF7:SFS1 se-
MF1: MF2: Bits per Sample Frequency/
F1 F2 Frame
SCLK
0
0
64
ratio to CLKIN sensed
0
1
128 ratio to CLKIN sensed
1
0
256 ratio to CLKIN sensed
1
1
256
fixed^†. = 256×Fs
† _{SCLK is master clock. CLKIN is not used. Not}
available in Multiplier Slave sub-mode.
Table 4. SM3-S/SM3-MS, Bits per Frame.
lecting the particular sub-frame. MF8:SFS2 must
be set to zero. See Figure 17.
When set for 256 SCLKs per frame (MF1:F1,
MF2:F2 = 10), four devices can occupy the se-
rial port. In this format both MF8:SFS2 and
MF7:SFS1 are used to select the particular sub-
frame.
In all three of the above slave sub-mode formats,
the frequency of the incoming SCLK signal, in
relation to the master clock provided on the
CLKIN pin, determines the sample frequency.
The CS4218 determines the ratio of SCLK to
CLKIN and sets the internal operating frequency
accordingly. Table 5 lists the SCLK to CLKIN
frequency ratio used to determine the codec’s
sample frequency. To obtain a given sample fre-
quency, SCLK must equal CLKIN divided by
the number in the table, based on the number of
bits per frame. As an example for SM3-S, as-
suming 64 BPF (bits per frame) and
CLKIN = 12.288 MHz, if a sample frequency of
24 kHz is desired, SCLK must equal CLKIN di-
vided by 8 or 1.536 MHz. A change in sample
rate automatically initiates a calibration cycle.
When MF1:F1 = MF2:F2 = 1, SCLK is used as
the master clock and is assumed to be 256 times
the sample frequency. In this mode, CLKIN is
SCLK to CLKIN Ratio Fs (kHz) Fs (kHz)
BPF BPF BPF with CLKIN with CLKIN
or 16xCLKIN or 16xCLKIN
256 128 64 12.288 MHz 11.2896 MHz
1
2
4
48.00
44.10
1.5
3
6
32.00
29.40
2
4
8
24.00
22.05
2.5
5
10
19.20
17.64
3
6
12
16.00
14.70
4
8
16
12.00
11.025
5
10 20
9.60
8.82
6
12 24
8.00
7.35
Table 5. SM3-S/SM3-MS, Fs Select.
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