CS4341 Datasheet, PDF (32/36 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
LRCK
SCLK
Left Channel
Right Channel
SDATA 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
Right Justified, 18-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
External SCLK Mode
Right Justified, 18-Bit DataData Valid on Rising Edge of
SCLKSCLK Must Have at Least 36 Cycles per LRCK
Period
Figure 26. CS4341 Format 6
Gain
dB
T1=50 µs
0dB
-10dB
T2 = 15 µs
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 27. De-Emphasis Curve
Left Channel
Audio Data
A Channel
Volume
Control
MUTE _AoutA
Right Channel
Audio Data
32
Σ
Σ
B Channel
Volume
Control
Figure 28. ATAPI Block Diagram
MUTE _AoutB
DS298PP2