CS4341 Datasheet, PDF (10/36 Pages) Cirrus Logic – 24-Bit, 96 kHz Stereo DAC with Volume Control

CS4341
SWITCHING CHARACTERISTICS - CONTROL PORT
(T_A = 25 °C; VA = +5 V ±5%; Inputs: logic 0 = AGND, logic 1 = VA, C_L = 30 pF)
Parameter
Symbol
Min
I²C^® Compatible Mode
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 11) t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of Both SDA and SCL Lines
t_r
-
Fall Time of Both SDA and SCL Lines
t_f
-
Setup Time for Stop Condition
t_susp
4.7
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
Notes: 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
RST
t _irs
Stop
Start
Repeated
Start
SDA
SCL
t _buf
t _hdst
t _high
t _hdst
tf
t _low t _hdd
t _sud
t _sust
tr
Figure 4. I²C Control Port Timing
Stop
t _susp
10
DS298PP2