CS2000-CP_09 Datasheet, PDF (30/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.3.4
CS2000-CP
Enable Device Configuration Registers 1 (EnDevCfg1)
This bit, in conjunction with EnDevCfg2, configures the device for control port mode. These EnDevCfg
bits can be set in any order and at any time during the control port access sequence, however they must
both be set before normal operation can occur.
EnDevCfg1
0
1
Application:
Register State
Disabled.
Enabled.
“SPI / I²C Control Port” on page 24
Note: EnDevCfg2 must also be set to enable control port mode. See “SPI / I²C Control Port” on
page 24.
8.4 Device Configuration 2 (Address 04h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
LockClk1
1
LockClk0
0
FracNSrc
8.4.1
Lock Clock Ratio (LockClk[1:0])
Selects one of the four stored User Defined Ratios for use in the dynamic ratio based Hybrid PLL Mode.
LockClk[1:0]
00
01
10
11
Application:
CLK_IN Ratio Selection
Ratio 0.
Ratio 1.
Ratio 2.
Ratio 3.
Section 5.3.2 on page 19
8.4.2
Fractional-N Source for Frequency Synthesizer (FracNSrc)
Selects static or dynamic ratio mode when auto clock switching is disabled.
FracNSrc
0
1
Application:
Fractional-N Source Selection
Static Ratio directly from R_EFF for Frequency Synthesizer Mode
Dynamic Ratio from Digital PLL for Hybrid PLL Mode
“Fractional-N Source Selection” on page 21
8.5 Global Configuration (Address 05h)
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Freeze
2
Reserved
1
Reserved
0
EnDevCfg2
8.5.1
Device Configuration Freeze (Freeze)
Setting this bit allows writes to the Device Control and Device Configuration registers (address 02h - 04h)
but keeps them from taking effect until this bit is cleared.
FREEZE
0
1
Device Control and Configuration Registers
Register changes take effect immediately.
Modifications may be made to Device Control and Device Configuration registers (registers 02h-04h) without
the changes taking effect until after the FREEZE bit is cleared.
30
DS761F1