CS2000-CP_09 Datasheet, PDF (29/36 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

8.2.3
PLL Clock Output Disable (ClkOutDis)
This bit controls the output driver for the CLK_OUT pin.
ClkOutDis
0
1
Application:
Output Driver State
CLK_OUT output driver enabled.
CLK_OUT output driver set to high-impedance.
“PLL Clock Output” on page 23
CS2000-CP
8.3 Device Configuration 1 (Address 03h)
7
RModSel2
6
RModSel1
5
RModSel0
4
RSel1
3
RSel0
2
1
0
AuxOutSrc1 AuxOutSrc0 EnDevCfg1
8.3.1
R-Mod Selection (RModSel[2:0])
Selects the R-Mod value, which is used as a factor in determining the PLL’s Fractional N.
RModSel[2:0]
000
001
010
011
100
101
110
111
Application:
R-Mod Selection
Left-shift R-value by 0 (x 1).
Left-shift R-value by 1 (x 2).
Left-shift R-value by 2 (x 4).
Left-shift R-value by 3 (x 8).
Right-shift R-value by 1 (÷ 2).
Right-shift R-value by 2 (÷ 4).
Right-shift R-value by 3 (÷ 8).
Right-shift R-value by 4 (÷ 16).
“Ratio Modifier (R-Mod)” on page 20
8.3.2
Ratio Selection (RSel[1:0])
Selects one of the four stored User Defined Ratios for use in the static ratio based Frequency Synthesizer
Mode.
RSel[1:0]
00
01
10
11
Application:
Ratio Selection
Ratio 0.
Ratio 1.
Ratio 2.
Ratio 3.
“User Defined Ratio (RUD), Frequency Synthesizer Mode” on page 19
8.3.3
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0]
00
01
10
11
Application:
Auxiliary Output Source
RefClk.
CLK_IN.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 23
Note: When set to 11, AuxLckCfg sets the polarity and driver type. See “AUX PLL Lock Output Config-
uration (AuxLockCfg)” on page 32.
DS761F1
29