CS4225 Datasheet, PDF (26/30 Pages) Cirrus Logic – Digital Audio Conversion System

CS4225
LRCK - Left/Right Select Signal I/O
The Left/Right select signal. This signal has a frequency equal to the sample rate. The
relationship of LRCK to the left and right channel data depends on the selected format.
RST-PDN - Reset and Power-Down Input
The CS4225 must be reset after power up by bringing this pin low, then high. To select power
down mode, float this pin, or drive this pin with a three-state buffer, and place the buffer in the
Hi-Z state. Low-to-high rise time should be less than 10µs.
DEM - De-emphasis Control
When high, DEM causes the standard Compact Disk de-emphasis frequency response for Fs =
44.1kHz to be applied to the DACs. If H/S is high, this pin is active. If H/S is low, then this pin
is enabled by setting the DEMC control bit to 0, and disabled by setting the DEMC control bit
to 1.
HOLD/DIF - Digital Interface Format Select Pin / HOLD Control
In software mode, when HOLD is high any time during the sample period, SDIN1 and SDIN2
data is ignored, and the previous "good" sample is presented to the DACs.
In hardware mode, DIF becomes a selection pin which selects audio data I/O formats 0, 1 and 2
(when IF0 is low) using a 3-level selection. Low selects format 0. High selects format 1.
Floating selects format 2. Float DIF by tying a 0.01µF capacitor from DIF to ground. In
hardware mode, both the auxiliary audio data port and the audio DSP port are set to the same
audio format.
SCL/CCLK/IF0 - Serial Control Interface Clock / DSP Interface Mode Select.
In software control mode, SCL/CCLK is the serial control interface clock, and is used to clock
control bits into and out of the CS4225.
In hardware control mode, when IF0 is low, the data for DACs 1 and 2 is input on SDIN1, and
for DACs 3 and 4 is input on SDIN2. The data from the audio ADCs is presented on SDOUT1
and the data from the 12-bit auxiliary ADC is presented on SDOUT2. In hardware control
mode, when IF0 is high, the data for all 4 DACs is input on the SDIN1 pin, and the data from
the audio ADCs and the 12-bit auxiliary ADC is output on the SDOUT1 pin. This mode allows
a DSP which has only 1 serial input and 1 serial output port to access all the DACs and ADCs.
AD3/CS/IF1 - Control Port Chip Select / Interface Control
In I²C^® software control mode, AD3 is a chip address bit. In SPI software control mode, CS is
used to enable the control port interface on the CS4225.
In hardware control mode, IF1 low sets the auxiliary digital audio input port to be master and
IF1 high sets the auxiliary digital audio input port to be slave. In slave mode, the PLL is used
to generate the internal 256 Fs clock from LRCKAUX, and to generate CLKOUT.
AD2/CDIN/CKF1 - Serial Control Data In / Interface Control
In I²C^® mode, AD2 is a chip address bit. In SPI software control mode, CDIN is the input data
line for the control port interface.
In hardware control mode, CKF0 and CKF1 controls the clock frequency of CLKOUT.
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