CS4225 Datasheet, PDF (12/30 Pages) Cirrus Logic – Digital Audio Conversion System

CS4225
nal PLL. The calibration that occurs following a
reset will proceed at a rate determined by the
free running VCO in software mode (which will
be at a Fs of about 40kHz), or the selected clock
input in hardware mode.
The CS4225 can be calibrated whenever desired.
A control bit, CAL, in the Control Byte, is pro-
vided to initiate a calibration. The sequence is:
1) Set CAL to 1, the CS4225 sets CALD to 1
and begins to calibrate.
2) Wait for CALD to go to 0. CALD will go to 0
when the calibration is done.
3) Set CAL to 0 for normal operation.
Clock Generation
The master clock to operate the CS4225 may be
generated by using the on-chip crystal oscillator,
by using the on-chip PLL, or by using an exter-
nal clock source. If the active clock source stops
for 5µs, the CS4225 will enter a power down
state to prevent overheating. In all modes it is
desirable to have SCLK & LRCK synchronous
to the selected master clock.
Clock Source
The CS4225 requires a high frequency (256 Fs)
clock to run the internal logic. The Clock Source
bits, CS0/1/2, in the Clock Mode Byte determine
the source of the clock. A high frequency crystal
can be attached to XTI and XTO, or a high fre-
quency clock can be input into XTI. In both
these cases, the internal PLL is disabled, with
the VCO shut off. The externally supplied high
frequency clock can be 256 Fs, 384 Fs or
512 Fs. The CI0/1 bits in the Clock Mode Byte
must be set accordingly. When using the on-chip
crystal oscillator, external loading capacitors are
required (see Figure 1). High frequency crystals
(> 8 MHz) should be parallel resonant, funda-
mental mode and designed for 20pF loading
(equivalent to 40pF to ground on each leg). An
example crystal supplier is CAL crystal
[phone].
12
Alternatively, the on-chip PLL may be used to
generate the required high frequency clock. The
PLL input clock is either 1 Fs, 32 Fs or 64 Fs
and may be input from the Auxiliary Port, (either
LRCKAUX or SCLKAUX), the DSP port,
(either LRCK or SCLK), or from XTI/XTO. In
this last case, a 1 Fs clock may be input into
XTI, or a 1 Fs crystal attached across XTI/XTO.
The gain of the internal inverter is adjusted for
the low crystal frequency. Using a clock at 64 Fs
will result in less PLL clock jitter than a clock at
1 Fs. The PLL will lock onto a new 1 Fs clock
within 5,000 Fs periods. If the PLL input clock
is removed, the VCO will drift to the low fre-
quency end of its frequency range.
In software mode, bits CS2/1/0 in the Clock
Mode Byte establish the clock source and fre-
quency. In Hardware mode, either LRCKAUX is
the clock reference, at 1 Fs, or the clock may be
input to XTI.
Master Clock Output
CLKOUT is a master clock output provided to
allow synchronization of external components.
Available CLKOUT frequencies of 1 Fs, 256 Fs,
384 Fs, and 512 Fs, are selectable by the CO0/1
bits of the Clock Mode Byte. When switching
between clock sources, CLKOUT will always re-
main low or high for > 10ns.
Synchronization
In normal operation, the DSP port and Auxiliary
port operate synchronously to the CS4225 clock
source. It is advisable to mute the DACs when
changing from one synchronization source to an-
other to avoid the output of undesirable audio
signals as the CS4225 resynchronizes. If data
which is not synchronous to the clock source is
input to the CS4225, then samples will be
dropped or repeated, which will cause audible
artifacts. Under such conditions, the CS4225
may not meet all data sheet performance specifi-
cations.
DS86PP8