CS2000-OTP Datasheet, PDF (25/30 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

6.3 Global Configuration Parameters
CS2000-OTP
6.3.1
6.3.2
Clock Skip Enable (ClkSkipEn)
This parameter enables clock skipping mode for the PLL and allows the PLL to maintain lock even when
the CLK_IN has missing pulses.
ClkSkipEn
0
1
Application:
PLL Clock Skipping Mode
Disabled.
Enabled.
“CLK_IN Skipping Mode” on page 11
Note: f_{CLK_IN} must be < 80 kHz to use this feature.
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = ‘11’), this
global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the
polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is dis-
regarded.
AuxLockCfg
0
1
Application:
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 19
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
6.3.3
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
RefClkDiv[1:0]
00
01
10
11
Application:
Reference Clock Input Divider
REF_CLK Frequency Range
÷ 4.
32 MHz to 75 MHz (50 MHz with XTI)
÷ 2.
16 MHz to 37.5 MHz
÷ 1.
8 MHz to 18.75 MHz
Reserved.
“Internal Timing Reference Clock Divider” on page 10
6.3.4
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
ClkOutUnl
0
1
Application:
Clock Output Enable Status
Clock outputs are driven ‘low’ when PLL is unlocked.
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
“PLL Clock Output” on page 19
DS758PP1
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