CS2000-OTP Datasheet, PDF(14/30 Page) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

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CS2000-OTP Datasheet, PDF (14/30 Pages) Cirrus Logic – Fractional-N Clock Synthesizer & Clock Multiplier

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CS2000-OTP

CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment

with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system

timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and

those synchronous to the PLL_OUT domain.

Wander < 128 Hz

CLK_IN

Jitter

PLL

PLL_OUT

BW = 128 Hz

Jitter > 128 Hz Rejected

Wander < 128 Hz Passed to Output

MCLK

LRCK

SCLK

Subclocks and data re-used

from previous clock domain.

LRCK

SCLK

SDATA

Figure 11. High bandwidth with CLK_IN domain re-use

While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock is

achieved, the digital loop bandwidth will settle to the minimum value selected by the ClkIn_BW[2:0] pa-

rameter.

Referenced Control

Parameter Definition

ClkIn_BW[2:0] .......................âClock Input Bandwidth (ClkIn_BW[2:0])â on page 26

5.4 Output to Input Frequency Ratio Configuration

5.4.1

User Defined Ratio (RUD), Frequency Synthesizer Mode

The User Defined Ratio, RUD, is a 32-bit un-signed fixed-point number which determines the basis for the

desired input to output clock ratio. Up to four different ratios, Ratio0-3, can be stored in the CS2000âs one

time programmable memory. Selection between the four ratios is achieved by the M[1:0] mode select

pins. The 32-bit RUD is represented in a high-resolution 12.20 format where the 12 MSBs represent the

integer binary portion while the remaining 20 LSBs represent the fractional binary portion. The maximum

multiplication factor is approximately 4096 with a resolution of 0.954 PPM in this configuration. See âCal-

culating the User Defined Ratioâ on page 27 for more information.

The status of internal dividers, such as the internal timing reference clock divider, are automatically taken

into account. Therefore RUD is simply the desired ratio of the output to input clock frequencies.

Referenced Control

Parameter Definition

Ratio 0-3................................âRatio 0 - 3â on page 24

M[1:0] ....................................âM1 and M0 Mode Pin Functionalityâ on page 20

5.4.2

User Defined Ratio (RUD), Hybrid PLL Mode

The same four ratio locations, Ratio0-3, are used to store the User Defined Ratios for Hybrid PLL Mode.

Selection of the User Defined Ratio for the dynamic ratio based Hybrid PLL Mode is made with the M[1:0]

pins (unless auto fractional N source selection is enabled; see section 5.4.6 on page 16).

In addition to the High-Resolution ratio format, a High-Multiplication format is also available. In the High-

Multiplication format mode, the 32-bit fixed-point number for RUD is represented in a 20.12 format where

the 20 MSBs represent the integer binary portion while the remaining 12 LSBs represent the fractional

DS758PP1

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