CS4328 Datasheet, PDF (24/31 Pages) Cirrus Logic – 18-Bit, Stereo D/A Converter for Digital Audio

CDB4328
master clock is to be used, U8 must be removed
from it’s socket to prevent the two clock signals
from interfering with one another. When 8412 is
selected by JP3, the master clock for the CS4328
is provided by the MCK output of the CS8412.
The CKS pin of the CS4328 can be pulled either
high or low via JP2. This determines whether
the master clock frequency has to be 384X or
256X the input word rate. Consult the CS4328
data sheet for the common master clock frequen-
cies table.
Analog Outputs
The analog outputs are available at 2 BNC con-
nectors labeled AOUTL and AOUTR. R5 and
C18 remove the remaining very high frequency
components from the left channel output signal
while R6 and C19 do so for the right channel
output signal.
Digital Audio Standard Interface
Included on the evaluation board is a CS8412
Digital Audio Interface Receiver. This device
can receive and decode data according to the
AES/EBU, S/PDIF, and EIAJ-340 interface
standard. Figure 3 shows the schematic for the
CS8412. The input is coupled to the device
through a transformer that is included on the
board. The input to the device can be configured
to accept either professional or consumer input
modes. Consult the CS8412 data sheet for an
explanation of the two input modes.
The LEDs, D4-D8, perform two functions.
When S1 is in the Channel Status position, the
LEDs display the channel status information for
the channel selected by JP1. When S1 is in the
Error Information position, the LEDs D4-D6,
display encoded error information that can be
decoded by consulting the CS8412 data sheet.
Encoded sample frequency information is dis-
played on LEDs D7-D9 provided a proper clock
is being applied to the FCK pin of JP1. When
an LED is lit, this indicates a "1" on the corre-
24
sponding pin located on the CS8412. When an
LED is off, this indicates a "0" on the corre-
sponding pin. Neither the L or R option should
be selected if the FCK pin of JP1 is being driven
by a clock signal.
Serial Output Interface
The SDATA, SCLK, L/R, and MCLK BNC
connectors can also be used to provide a serial
output interface for the CS8412. With JP3 in the
8412 position, the outputs from the CS8412 can
be brought off the board to an external evalution
system. This data can be configured in one of
seven selectable formats. These formats are out-
lined in the CS8412 data sheet.
CDB5336/7/8/9 Interface to CDB4328
Many users find it informative to evaluate a
combined ADC and DAC system connected to-
gether yielding analog input and analog output.
This can be accomplished by interconnecting a
CDB5326/7/8/9 or CDB5336/7/8/9 to a
CDB4328 evaluation board. The following in-
formation contains several techniques to
accomplish this goal. There are two general
points which need to be mentioned. An analog
input of ± 3.68 V will produce a full scale digital
output from the CS5336/7/8/9 and the
CS5326/7/8/9. A full scale digital input to the
CS4328 will produce a full scale output of ± 2 V
resulting in an overall loss of approximately
5.2 dB from input to output. Also it is recom-
mended that the power connections for each
board are brought directly from the power sup-
ply and not in a "daisy-chain" manner from
board to board.
Connecting the CDB4328 to the CDB5336/7/8/9
can be accomplished using one of two methods:
DS62DB2