CS4328 Datasheet, PDF (17/31 Pages) Cirrus Logic – 18-Bit, Stereo D/A Converter for Digital Audio

CS4328
Digital Inputs
XTI - Crystal or Clock Input, PIN 14.
A crystal oscillator can be connected between this pin and XTO, or an external CMOS clock
can be input on XTI. The frequency must be either 256× or 384× the input word rate based on
the clock select pin, CKS.
ACKI - Analog Clock Input, PIN 24.
This is the master clock input for the analog section of the chip and must be 128× the input
word rate. ACKI is typically connected to the Analog Clock Ouput pin, ACKO.
CALI - Calibration Input, PIN 27.
Input to the analog section that is used during offset calibration. Normally connected to the
Calibration Output pin, CALO.
CMPI - Comparator Input, PIN 8
Input to the digital section that is used during offset calibration. Normally connected to the
Comparator Output pin, CMPO.
LRCK - Left/Right Clock, PIN 20.
This input determines which channel is currently being input on the Serial Data Input pin,
SDATAI. The format of LRCK is controlled by DIF0 and DIF1.
BICK - Serial Bit Input Clock, PIN19.
Clocks the individual bits of the serial data in from the SDATAI pin. The edge used to latch
SDATAI is controlled by DIF0 and DIF1.
SDATAI - Serial Data Input, PIN 18.
Two’s complement MSB-first serial data of either 16 or 18 bits is input on this pin. The data is
clocked into the CS4328 via the BICK clock and the channel is determined by the LRCK clock.
The format for the previous two clocks is determined by the Digital Input Format pins, DIF0
and DIF1
DIF0,DIF1 - Digital Input Format, PINS 13, 12
These two pins select one of four formats for the incoming serial data stream. These pins set
the format of the BICK and LRCK clocks with respect to SDATAI. The formats are listed in
Table 2.
CKS - Clock Speed Select, PIN 11.
Selects the clock frequency input on the XTI pin. CKS low selects 256× the input word rate
(LRCK frequency) while CKS high selects 384×.
RST - Reset and Calibrate, PIN 9.
When reset is low the filters and modulators are held in reset. When reset goes high, an offset
calibration is initiated.
DS62F3
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