CS4328 Datasheet, PDF (23/31 Pages) Cirrus Logic – 18-Bit, Stereo D/A Converter for Digital Audio

CDB4328
U3, Pin 3
U3, Pin 6
U3, Pin 8
U3, Pin 11
VD+
+
1 uF
C26
0.1 uF
C25
16 22
24 3
7
VD+
NC
ACKO
ACKI
VA+
23
NC
TP 20 _LRCK
TP 19
BICK
TP _{18 SDATAI}
TP ₁₄
XTI
U1
CS4328
L/R SCLK SDATA MCLK
15 _XTO
From
Reset
Circuit
9 _RST
TST DGND CKS
10 17 11
DIFO
13
AGND1 ¹
VA- ⁵
AGND2 ⁴
C23
+ _C24
+5V Analog,
VA+
0.1 uF _{1.0 uF}
C22
0.1 uF
C21
0.1 uF
-5V Analog,
+
C20 _VA-
1.0 uF
AGND3 ²⁵
CMPO ⁶
CMPI ⁸
CALO ²¹
27
CALI
2 ^R5
AOUTL
51Ω
TP
AOUTL
C18
10 nF NPO
26 ^R6
AOUTR
51Ω
28
VREF
DIFI
12
C16
0.1 uF
TP
C19
AOUTR
10 nF NPO
C17
10 uF ⁺
JP2
R11
47kΩ
VD+
VD+
Figure 2. CS4328 DAC Connections
The CS4328 supports four serial data input for-
mats. The selection of which is made via the
digital input format pins DIF0 and DIF1. The
different formats control the relationship of L/R
to SDATA and the edge of SCLK used to latch
the data. Consult the CS4328 data sheet for an
explanation of the different formats.
Position
EXT CLK
8412
Input Option Selected
SDATA,SCLK, L/R provided
by an external source.
SDATA,SCLK, L/R provided
by the CS8412
Table 1. JP3 Selectable Options
System Timing
The master clock input to the CS4328 can be
provided by several sources. JP3 selects the
source of the master clock that is to be supplied
to the XTI pin of the converter. When EXT
CLK is selected, the master clock is provided by
one of two sources. The 12.288 MHz clock sig-
nal provided by U8 can be used as the master
clock for both the CS4328 and the external sys-
tem that provides the serial data to the board.
The other option is for a master clock that is
synchronized to the external serial data coming
into the board, be used as the master clock for
the CS4328 as well. However, if an external
DS62DB2
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