CS4207-CNZ Datasheet, PDF (22/148 Pages) Cirrus Logic – Low-power, 4-in / 6-out HD Audio Codec with Headphone Amp

CS4207
DIGITAL MICROPHONE INTERFACE CHARACTERISTICS
Test conditions: Inputs: Logic 0 = GND = 0 V, Logic 1 = VL_IF; T_A = +25 C; C_LOAD = 30 pF.
Parameters
Symbol
Min
DMIC_SCL Period (Fs_ADC >= 44.1 kHz)
DMIC_SCL Period (Fs_ADC <= 32.0 kHz)
DMIC_SCL Duty Cycle
(Note 12)
t_P
-
(Note 12)
t_P
-
-
45
DMIC_SCL Rise Time
(Note 13)
t_r
-
DMIC_SCL Fall Time
(Note 13)
t_f
-
DMIC_SDA Setup Time Before DMIC_SCL Rising Edge
t_s(SD-CLKR)
40
DMIC_SDA Hold Time After DMIC_SCL Rising Edge
t_h(CLKR-SD)
5
DMIC_SDA Setup Time Before DMIC_SCL Falling Edge
t_s(SD-CLKF)
40
DMIC_SDA Hold Time After DMIC_SCL Falling Edge
t_h(CLKF-SD)
6
Typ
8 • T_cyc
12 • T_cyc
-
-
-
-
-
-
-
Max
-
-
55
10
10
-
-
-
-
Units
ns
ns
%
ns
ns
ns
ns
ns
ns
Notes:
12. The output clock frequency will follow the Bit Clock (BITCLK) frequency divided by 8 or 12, depending on
the sample rate of the ADC. Any deviation of the Bit Clock source from the nominal supported rates will be
directly imparted to the output clock rate by the same factor (e.g. +100 ppm offset in the frequency of BIT-
CLK will become a +100 ppm offset in DMIC_SCL). For the nominal value of T_cyc reference HDA024-A
(see Note 4 in “References” on page 147).
13. Rise and fall times are measured from 0.1 • VL_IF to 0.9 • VL_IF.
t_P
t_f
t_r
DMIC_SCL
t_s(SD-CLKF) t_s(SD-CLKR)
DMIC_SDA
Left
(A, DATA1)
Channel Data
Right
(B, DATA2)
Channel Data
Left
(A, DATA1)
Channel Data
t_h(CLKF-SD)
Figure 7. Digital MIC Interface Timing
t_h(CLKR-SD)
22
DS880F4