CS4207-CNZ Datasheet, PDF (143/148 Pages) Cirrus Logic – Low-power, 4-in / 6-out HD Audio Codec with Headphone Amp

CS4207
2. set the DMIC1 Enable and/or DMIC2 Enable bit in the Beep Configuration (CIR = 0004h) register of
the Vendor Processing Widget (Node ID = 11h)
3. set the INE bit in the Pin Widget Control of the Digital Mic In 1 Pin Widget (Node ID = 0Eh) and/or the
Digital Mic In 2 Pin Widget (Node ID = 12h)
4. for DMIC1 set the Connection Index in the ADC2 Connection Select Control of the ADC2 Input Con-
verter Widget (Node ID = 06h) to a value of 01h
5. for DMIC2 set the Connection Index in the ADC1 Connection Select Control of the ADC1 Input Con-
verter Widget (Node ID = 05h) to a value of 01h
The clock signal for the DMIC interface (DMIC_SCL) will be enabled if at least one of the DMIC data paths
has been configured as described above.
7.5 S/PDIF Input and Outputs
7.5.1
S/PDIF Receiver SRC
The S/PDIF Receiver SRC is used to sample-rate convert incoming source-synchronous data to HDA
bus-synchronous data. The SRC can only convert rates that are close to one another, therefore, software
must monitor the Recovered Sample Rate in the S/PDIF RX/TX Interface Status (CIR = 0000h) register
and program the Converter Format Control of the S/PDIF Receiver Input Converter Widget (Node ID =
07h) accordingly.
The S/PDIF Receiver SRC is on by default and will be turned off if at least one of the following conditions
is true:
– TYPE (bit 15) in the Converter Format Control of the S/PDIF Receiver Input Converter Widget (Node
ID = 07h) is set to ‘1’.
– RX Raw Data Mode (bit 6) in the S/PDIF RX/TX Interface Control (CIR = 0001h) register is set to ‘1’.
DS880F4
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