CS2100-OTP_09 Datasheet, PDF (21/26 Pages) Cirrus Logic – Fractional-N Clock Multiplier

6.1.2
CS2100-OTP
Auxiliary Output Source Selection (AuxOutSrc[1:0])
Selects the source of the AUX_OUT signal.
AuxOutSrc[1:0]
00
01
10
11
Application:
Auxiliary Output Source
RefClk.
CLK_IN.
CLK_OUT.
PLL Lock Status Indicator.
“Auxiliary Output” on page 17
Note: When set to 11, the AuxLockCfg global parameter sets the polarity and driver type (“AUX PLL
Lock Output Configuration (AuxLockCfg)” on page 21).
6.2 Ratio 0 - 3
The four 32-bit User Defined Ratios are stored in the CS2100’s one time programmable memory. See “Out-
put to Input Frequency Ratio Configuration” on page 14 and “Calculating the User Defined Ratio” on
page 23 for more details.
6.3 Global Configuration Parameters
6.3.1
AUX PLL Lock Output Configuration (AuxLockCfg)
When the AUX_OUT pin is configured as a lock indicator (AuxOutSrc[1:0] modal parameter = ‘11’), this
global parameter configures the AUX_OUT driver to either push-pull or open drain. It also determines the
polarity of the lock signal. If AUX_OUT is configured as a clock output, the state of this parameter is dis-
regarded.
AuxLockCfg
0
1
Application:
AUX_OUT Driver Configuration
Push-Pull, Active High (output ‘high’ for unlocked condition, ‘low’ for locked condition).
Open Drain, Active Low (output ‘low’ for unlocked condition, high-Z for locked condition).
“Auxiliary Output” on page 17
Note: AUX_OUT is an unlock indicator, signalling an error condition when the PLL is unlocked. There-
fore, the pin polarity is defined relative to the unlock condition.
6.3.2
Reference Clock Input Divider (RefClkDiv[1:0])
Selects the input divider for the timing reference clock.
RefClkDiv[1:0]
00
01
10
11
Application:
Reference Clock Input Divider
REF_CLK Frequency Range
÷ 4.
32 MHz to 75 MHz (50 MHz with XTI)
÷ 2.
16 MHz to 37.5 MHz
÷ 1.
8 MHz to 18.75 MHz
Reserved.
“Internal Timing Reference Clock Divider” on page 11
DS841F1
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