CS2100-OTP_09 Datasheet, PDF (1/26 Pages) Cirrus Logic – Fractional-N Clock Multiplier

CS2100-OTP
Fractional-N Clock Multiplier
Features
 Clock Multiplier / Jitter Reduction
– Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
 Highly Accurate PLL Multiplication Factor
– Maximum Error Less Than 1 PPM in High-
Resolution Mode
 One-Time Programmability
– Configurable Hardware Control Pins
– Configurable Auxiliary Output
 Flexible Sourcing of Reference Clock
– External Oscillator or Clock Source
– Supports Inexpensive Local Crystal
 Minimal Board Space Required
– No External Analog Loop-filter
Components
General Description
The CS2100-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2100-OTP is based on a hybrid analog-
digital PLL architecture comprised of a unique combina-
tion of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external
noisy synchronization clock with frequencies as low as
50 Hz. The CS2100-OTP has many configuration op-
tions which are set once prior to runtime. At runtime
there are three hardware configuration pins available for
mode and feature selection.
The CS2100-OTP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) grade. Customer
development kits are also available for custom device
prototyping, small production programming, and device
evaluation. Please see “Ordering Information” on
page 26 for complete details.
Hardware
Control
Hardware Configuration
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
8 MHz to 75 MHz
Low-Jitter Timing
Reference
50 Hz to 30 MHz
Frequency
Reference
Output to Input
Clock Ratio
http://www.cirrus.com
Fractional-N
Frequency Synthesizer
N
Digital PLL &
Fractional N Logic
Copyright  Cirrus Logic, Inc. 2009
(All Rights Reserved)
Auxiliary
Output
6 to 75 MHz
PLL Output
AUG '09
DS841F1