CS42518_05 Datasheet, PDF (20/91 Pages) Cirrus Logic – 110 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

3. TYPICAL CONNECTION DIAGRAM
CS42518
+3.3 V to +5 V
+ 0.1 µF 0.01 µF
10 µF
0.01 µF 0.1 µF ₊
10 µF
+5 V
+2.5 V
to +5 V
+1.8 V
to +5 V
+ 0.1 µF 0.01 µF
10 µF
0.01 µF 0.1 µF ₊
10 µF
D riv e r
S /P D IF
Interface
Up to 8
Sources
OSC
CS5361
A/D Converter
CS5361
A/D Converter
4
51
VD
VD
50 _TXP
49 _RXP0
48 _RXP1/GPO1
47 _RXP2/GPO2
46 _RXP3/GPO3
45 _RXP4/GPO4
44 _RXP5/GPO5
43 _RXP6/GPO6
42 _RXP7/GPO7
53
VLS
0.1 µF
41
24
VA
VA
36
AOUTA1+
37
AOUTA1-
35
AOUTB1+
34
AOUTB1-
32
AOUTA2+
33
AOUTA2-
AOUTB2+ ³¹
30
AOUTB2-
59 _OMCK
58 _ADCIN1
57 _ADCIN2
55
RMCK
CS42518
AOUTA3+ ²⁸
29
AOUTA3-
AOUTB3+ ²⁷
AOUTB3- ²⁶
Analog Output Buffer ²
and
M ute Circuit (optional)
Analog Output Buffer ²
and
M ute Circuit (optional)
Analog Output Buffer ²
and
M ute Circuit (optional)
Analog Output Buffer ²
and
M ute Circuit (optional)
Analog Output Buffer ²
and
M ute Circuit (optional)
Analog Output Buffer ²
and
M ute Circuit (optional)
Digital Audio
P ro c e s s o r
54
S A I_S D O U T
60
S A I_ L R C K
61
S A I_ S C L K
3 _{CX_LRCK}
2
CX_SCLK
56 _{CX_SDOUT}
1 _{CX_SDIN1}
64 _{CX_SDIN2}
63 _{CX_SDIN3}
62 _{CX_SDIN4}
M icro-
C o n tro lle r
2 kΩ
11
12
7
8
9
10
**
**
2 kΩ
6
0.1 µF
INT
RST
S C L/C C L K
S D A /C D O U T
A D 1 /C D IN
A D 0 /C S
VLC
22
AOUTA4+
AOUTA4- ²³
Analog Output Buffer ²
and
M ute Circuit (optional)
21
AOUTB4+
AOUTB4- ²⁰
+VA
38 *
MUTEC
*
15
A IN L +
16
AINL-
Analog Output Buffer ²
and
M ute Circuit (optional)
M ute
D riv e
(optional)
A n a lo g
2I7n0p0utpF *
Buffer ¹
* Pull up or down as
required on startup if the
M ute C ontrol is used.
Left Analog Input
14
A IN R +
13
AINR-
A n a lo g
2I7n0p0utpF *
Buffer ¹
Right Analog Inpu
VQ ¹⁷
FILT+ ¹⁸
REFGND ¹⁹
39
LPFLT
+
0.1 µF 100 µF
RFILT ³
+
0.1 µF 4.7 µF
** Resistors are required for
I²C control port operation
DGND DGND
5
52
AGND
25
AGND
40
CFILT ³ CRIP ³
Connect D G ND and A G ND at single point near C odec
1. See the ADC Input Filter section in the Appendix.
2. See the DAC O utput Filter section in the Appendix.
3. See the PLL Filter section in the Appendix.
Figure 5. Typical Connection Diagram
20
DS584F1