CS4298 Datasheet, PDF (19/52 Pages) Cirrus Logic – SoundFusion Audio/Modem Codec 97 (AMC 97)

CS4298
5.4.2 Read-Back Address Port (Slot 1)
Bit 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3210
RI6 RI5 RI4 RI3 RI2 RI1 RI0
RI[6:0]
Register index. The Read-Back Address Port echoes the AC ’97 Register address when a register read
has been requested in the previous frame. The Codec will only echo the register index for a read access.
Write accesses will not return valid data in Slot 1.
5.4.3 Read-Back Data Port (Slot 2)
Bit 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
RD[15:0]
16-bit register value. The Read-Back Data Port contains the register data requested by the Controller
from the previous read request. All read requests will return the read address in the Read-Back Address
Port (Slot 1) and the register data in the Read-Back Data Port (Slot 2) on the following serial data frame.
5.4.4 PCM Capture Data (Slot 3-11)
Bit 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CD17 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD9 CD8 CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
CD[17:0] 18-bit PCM (2’s compliment) data. The mapping of a given slot to an ADC is determined by the state of
the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register.
5.4.5 GPIO Pin Status (Slot 12)
Bit 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
GI9 GI8 GI7 GI6 GI5 GI4 GI3 GI2 GI1 GI0
IRQ
GI[9:0] Status of the GPIO[9:0] pin.
IRQ
Set when the GPIO generates a wake up or interrupt cycle. See GPIO Pin Wake Up Mask (Index 52h)
register.
The capture data in Slot [3:12] will only be valid when the respective slot valid bit is set in Slot 0.
DS315PP2
19