CS4298 Datasheet, PDF (18/52 Pages) Cirrus Logic – SoundFusion Audio/Modem Codec 97 (AMC 97)

CS4298
5.3.3 Register Write Data (Slot 2)
Bit 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4 3210
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
WD[15:0]
Codec register data for write operations. For read operations, this data is ignored. If R/W# = 0, data must
be valid in both the Register Address (Slot 1) and the Register Write Data (Slot 2) during a frame when
the Slot [1:2] Valid = 11 or either SCRA[1:0] bit is set. Splitting the register address and the write data
across multiple frames is not permitted.
5.3.4 Playback Data (Slots 3-11)
Bit 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PD19 PD18 PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
PD[19:0]
20-bit PCM playback (2’s compliment) data for the left and right DACs, S/PDIF transmitter, or GPIO
pins. Any PCM data from the Controller less than 20 bits should be left justified in the slot and zero-
padded. Table 9 on page 35 lists the definition of each respective slot. The mapping of a given slot is
determined by the MD[1:0] bits found in the AC Mode Control (Index 5Eh) register.
5.3.5 GPIO Data (Slot12)
Bit 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
GP9 GP8 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
GP[9:0] GPIO Output Date. Output data is transferred to the GPIO pins every frame in Slot 12.
5.4 AC-Link Audio Input Frame
In the serial data input frame, data is passed on the SDATA_IN pin FROM the CS4298 to the AC ’97
Controller. The data format for the input frame is very similar to the output frame. Figure 9 illustrates
the serial port timing.
5.4.1 Serial Data Input Slot Tag Bits (Slot 0)
Bit 15 14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Codec Slot 1 Slot 2 Slot 3 Slot 4 Slot 5 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10 Slot 11 Slot 12
Ready Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid
Codec ReadyIndicates the readiness of the CS4298’s AC-link and Control and Status registers. Immediately after a
Cold Reset this bit will be clear. Once the CS4298’s clocks and voltages are stable, this bit will be set.
Until the Codec Ready bit is set, no AC-link transactions should be attempted by the Controller. The
Codec Ready bit does not indicate readiness of the DACs, ADCs, Vref, or any other analog function.
Those must be checked in the Power Down Control/Status (Index 26h), Ext’d Audio Ctrl/Stat (Index
2Ah), and Ext’d Modem Ctrl/Stat (Index 3Eh) registers by the Controller before any access is made to
the mixer registers. Any accesses to the Codec while Codec Ready is clear is ignored.
Slot 1 Valid Tag
Indicates Slot 1 contains a valid read back address.
Slot 2 Valid Tag
Indicates Slot 2 contains valid register read data.
Slot [3:11] Valid Tag
Indicates Slot [3:11] contains valid capture data from the Codec’s ADC.
Slot 12 Valid Tag
Indicates Slot 12 contains valid read data of the GPIO Pin Status Register (Index 54h).
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DS315PP2