CS42416_05 Datasheet, PDF (18/73 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with PLL

3. TYPICAL CONNECTION DIAGRAMS
+3.3 V to +5 V
+ 0.1 µF 0.01 µF
10 µF
CS42416
0.01 µF 0.1 µF ₊
10 µF
+5 V
+3.3 V
to +5.0 V
Optional
S/PDIF
OSC
+ 0.1 µF 0.01 µF
10 µF
0.01 µF 0.1 µF ₊
10 µF
CS8416
Receiver
RMCK
4
51
VD
VD
48 _GPO1
47 _GPO2
46 _GPO3
45 _GPO4
44 _GPO5
43 _GPO6
42 _GPO7
41
24
VA
VA
36
AOUTA1+
37
AOUTA1-
35
AOUTB1+
34
AOUTB1-
32
AOUTA2+
33
AOUTA2-
Analog Output Buffer ²
and
Mute Circuit (optional)
Analog Output Buffer ²
and
Mute Circuit (optional)
Analog Output Buffer ²
and
Mute Circuit (optional)
CS5361
A/D Converter
CS5361
A/D Converter
Digital Audio
Processor
53
VLS
0.1 µF
59 _OMCK
58 _ADCIN1
57 _ADCIN2
55
RMCK
CS42416
56 _{ADC_SDOUT}
60
ADC_LRCK
61
ADC_SCLK
3 _{DAC_LRCK}
2
DAC_SCLK
1 _{DAC_SDIN1}
64 _{DAC_SDIN2}
63 _{DAC_SDIN3}
AOUTB2+ ³¹
30
AOUTB2-
AOUTA3+ ²⁸
29
AOUTA3-
AOUTB3+ ²⁷
AOUTB3- ²⁶
Analog Output Buffer ²
and
Mute Circuit (optional)
Analog Output Buffer ²
and
Mute Circuit (optional)
Analog Output Buffer ²
and
Mute Circuit (optional)
+VA
38 *
MUTEC
*
Mute
Drive
(optional)
* Pull up or down as
required on startup if the
Mute Control is used.
15
AINL+
AINL- ¹⁶
Analog
2I7n0p0utpF*
Buffer ¹
Left Analog Input
+1.8V
to +5V
Micro-
Controller
2 kΩ
11
INT
12
RST
7
SCL/CCLK
8
SDA/CDOUT
9
AD1/CDIN
10 _AD0/CS
**
**
2 kΩ
6
VLC
0.1 µF
14
AINR+
13
AINR-
Analog
2I7n0p0utpF*
Buffer ¹
Right Analog Input
VQ ¹⁷
FILT+ ¹⁸
REFGND ¹⁹
39
LPFLT
+
0.1 µF 100 µF
RFILT ³
+
0.1 µF 4.7 µF
** Resistors are required for
I²C control port operation
DGND DGND
5 52
AGND AGND
25
40
CFILT ³ CRIP ³
Connect DGND and AGND at single point near Codec
1. See the ADC Input Filter section in the Appendix.
2. See the DAC Output Filter section in the Appendix.
3. See the PLL Filter section in the Appendix.
Figure 5. Typical Connection Diagram
18
DS602F1