CS42416_05 Datasheet, PDF (13/73 Pages) Cirrus Logic – 110 dB, 192 kHz 6-Ch Codec with PLL

CS42416
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI^™ FORMAT
(For CQZ, T_A = -10 to +70° C; For DQZ, T_A = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
Inputs: Logic 0 = DGND, Logic 1 = VLC, C_L = 30 pF)
Parameter
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol Min Typ Max Units
f_sck
t_csh
t_css
t_scl
t_sch
t_dsu
(Note 20)
t_dh
t_pd
t_r1
t_f1
(Note 21)
t_r2
(Note 21)
t_f2
0
-
6.0
MHz
1.0
-
-
µs
20
-
-
ns
66
-
-
ns
66
-
-
ns
40
-
-
ns
15
-
-
ns
-
-
50
ns
-
-
25
ns
-
-
25
ns
-
-
100
ns
-
-
100
ns
Notes:
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For f_sck <1 MHz.
CS
t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
CDOUT
t _dsu
t _dh
t _pd
Figure 4. Control Port Timing - SPI Format
DS602F1
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