CS4228 Datasheet, PDF (16/30 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228
64 clks
64 clks
LRCK
Left Channel
Right Channel
SCLK
SDIN1/2/3 MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
LSB
MSB
DAC1
DAC3
DAC5
DAC2
DAC4
DAC6
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
SDOUT
ADCL
ADCR
20 clks
20 clks
One Line Data Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Notes
20
128 Fs
6 inputs, 2 outputs, BRM only
Figure 12. One Line Data Serial Audio Format
The control port has 2 operating modes: SPI and
I²C compatible. In both modes the CS4228 oper-
ates as a slave device. Mode selection is deter-
mined by the state of the SDOUT pin when RST
transitions from low to high: high for SPI, low for
I²C. SDOUT is internally pulled high to VL. A re-
sistive load from SDOUT to DGND of less than 47
kΩ will enable I²C Mode after a reset.
SPI Mode
In SPI mode, CS is the CS4228 chip select signal,
CCLK is the control port bit clock input, and CDIN
is the input data line. There is no data output line,
therefore all registers are write-only in SPI mode.
Data is clocked in on the rising edge of CCLK.
Figure 13 shows the operation of the control port in
SPI mode. The first 7 bits on CDIN, after CS goes
low, form the chip address (0010000). The eighth
bit is a read/write indicator (R/W), which should be
low to write. The next 8 bits set the Memory Ad-
dress Pointer (MAP) which is the address of the
register that is to be written. The following bytes
contain the data which will be placed into the reg-
isters designated by the MAP.
The CS4228 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is zero, then the MAP will stay constant for
successive reads or writes. If INCR is 1, then MAP
will increment after each byte is read or written, al-
lowing block reads or writes of successive regis-
ters.
I²C Mode
In I²C mode, SDA is a bidirectional data line. Data
is clocked into and out of the port by the SCL clock.
The signal timing is shown in Figure 14. The AD0
pin forms the LSB of the chip address. The upper 6
bits of the 7 bit address field must be 001000. To
communicate with a CS4228, the LSB of the chip
address field, which is the first byte sent to the
CS4228 after a Start condition, should match the
setting of the AD0 pin. The eighth bit of the address
bit is the R/W bit (high for a read, low for a write).
When writing, the next byte is the Memory Ad-
dress Pointer (MAP) which selects the register to
be read or written. If the operation is a read, the
contents of the register pointed to by the MAP will
be output. Setting the auto increment bit in the
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DS307PP1