CS4228 Datasheet, PDF (14/30 Pages) Cirrus Logic – 24-Bit, 96 kHz Surround Sound Codec

CS4228
Clock Generation
The master clock, MCLK, is supplied to the
CS4228 from an external clock source. If MCLK
stops for 10µs, the CS4228 will enter Power Down
Mode in which the supply current is reduced as
specified under “Power Supply” on page 6. In all
modes it is required that the number of MCLK pe-
riods per SCLK and LRCK period be constant.
Clock Source
The CS4228 internal logic requires an external
master clock, MCLK, that operates at multiples of
the sample rate frequency, Fs. The MCLK/Fs ratio
is determined by the CI1:0 bits in the CODEC
Clock Mode register.
Synchronization
The serial port is internally synchronized with
MCLK. If from one LRCK cycle to the next, the
number of MCLK cycles per LRCK cycle changes
by more than 32, the CS4228 will undergo an inter-
nal reset of its data paths in an attempt to resyn-
chronize. Consequently, it is advisable to mute the
DACs when changing from one clock source to an-
other to avoid the output of undesirable audio sig-
nals as the device resynchronizes.
Digital Interfaces
Serial Audio Interface Signals
The serial audio data is presented in 2's comple-
ment binary form with the MSB first in all formats.
The serial interface clock, SCLK, is used for both
transmitting and receiving audio data. SCLK can
be generated by the CS4228 (master mode) or it
can be input from an external source (slave mode).
Mode selection is made with the DMS1:0 bits in
the Serial Port Mode register. The number of
SCLK cycles in one sample period can be set using
the DCK1:0 bits as detailed in the Serial Port Mode
register.
The Left/Right clock (LRCK) is used to indicate
left and right data frames and the start of a new
sample period. It may be an output of the CS4228
(master mode), or it may be generated by an exter-
nal source (slave mode). The frequency of LRCK is
the same as the system sample rate, Fs.
SDIN1, SDIN2, and SDIN3 are the data input pins.
SDOUT, the data output pin, carries data from the
two 24-bit ADC's. The serial audio port may also
be operated in One Line Data Mode in which all 6
channels of DAC data is input on SDIN1 and the
stereo ADC data is output on SDOUT. Table 1 out-
lines the serial port input to DAC channel alloca-
tions.
DAC Inputs
SDIN1
left channel
right channel
single line
DAC #1
DAC #2
All 6 DAC channels
SDIN2 left channel DAC #3
right channel DAC #4
SDIN3 left channel DAC #5
right channel DAC #6
Table 1. Serial Audio Port Input Channel Allocations
Serial Audio Interface Formats
The digital audio port supports 6 formats, shown in
Figures 9, 10, 11 and 12. These formats are selected
using the DDF2:0 bits in the Serial Port Mode reg-
ister.
In One Line Data Mode, all 6 DAC channels are in-
put on SDIN1. One Line Data Mode is only avail-
able in BRM. See Figure 12 for channel
allocations.
Control Port Signals
Internal registers are accessed through the control
port. The control port may be operated asynchro-
nously with respect to audio sample rate. However,
to avoid potential interference problems, the con-
trol port pins should remain static if no register ac-
cess is required.
14
DS307PP1