CS22210 Datasheet, PDF (12/31 Pages) Cirrus Logic – WIRELESS PCI/USB CONTROLLER

Digital Wireless Radio Interface
All radio input buffers are Schmitt triggered input buffers. There are total of 21 signals in this
interface.
TXCLK
Input
Transmit clock is a clock input from the radio baseband processor. This
signal is used to clock out the transmit data on the rising edge of TXCLK.
TXPEBB
Output
Baseband transmit power enable, an output from the MAC to the radio
baseband processor. When active, the baseband processor transmitter is
configured to be operational, otherwise the transmitter is in standby mode.
TXD
Output
It is the serial data output from the MAC to the radio baseband processor.
The data is transmitted serially with the LSB first. The data is driven by the
MAC on the rising edge of TXCLK and is sampled by the radio baseband
processor on the falling edge of TXCLK (in 3824 mode) and rising edge of
TXCLK (in 3860B mode).
TXRDY
Input
Transmit data ready is an input to the MAC from the radio baseband
processor to indicate that the radio baseband processor is ready to
receive the data packet over the TXD signal. The signal is sampled by the
MAC on the rising edge of TXCLK.
CCA
Input
Clear channel assessment is an input from the radio baseband processor
to signal that the channel is clear to transmit. When this signal is a 0, the
channel is clear to transmit. When this signal is a 1, the channel is not
clear to transmit. This helps the MAC to determine when to switch from
receive to transmit mode.
BBRNW
Output
Baseband read/write is an output from the MAC to indicate the direction of
the SD bus when used for reading or writing data. This signal has to be
set up to the rising edge of BBSCLK for the baseband processor and is
driven on the falling edge of BBSCLK.
NRESETBB
Output
Baseband reset is an output of the MAC to reset the baseband processor.
CS22210 PCI/USB Wireless Controller
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