WM8235 Datasheet, PDF (11/154 Pages) Wolfson Microelectronics plc – 70MSPS 9-Channel AFE with Sensor Timing Generation and LVDS/CMOS Data Output

WM8235
INTERNAL POWER ON RESET CIRCUIT
AVDD
VDD
LDOOUT
Power On Reset
Circuit
T
GND
INTERNAL PORB
AGND
Figure 1 Internal Power On Reset Circuit Schematic
The WM8235 includes an internal Power-On-Reset Circuit, as shown in Figure 1, which is used reset
the digital logic into a default state after power up. The POR circuit is powered from AVDD and
monitors LDOOUT. It asserts PORB low if AVDD or LDOOUT is below a minimum threshold.
LDOOUT
LDOGND
Vpord_on
AVDD
Vpora
AGND
HI
INTERNAL PORB
LO
No Power
POR
Internal
POR active
Undefined
Device Ready
Vpora_off
Internal POR active
Figure 2 Typical Power up Sequence where AVDD is Powered before LDOOUT
Figure 2 shows a typical power-up sequence where AVDD is powered up first. When AVDD rises
above the minimum threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is
asserted low and the chip is held in reset. In this condition, all writes to the control interface are
ignored. When LDOOUT rises to Vpord_on, PORB is released high and all registers are in their
default state and writes to the control interface may take place. On power down, where AVDD falls
first, PORB is asserted low whenever AVDD drops below the minimum threshold Vpora_off.
SYMBOL
MIN
TYP
MAX
Vpora
0.4
0.6
0.8
Vpora_off
0.4
0.6
0.8
Vpord_on
0.5
0.7
0.9
Table 1 Typical POR Operation (typical values, not tested)
UNIT
V
V
V
Rev 4.6
11