CS3865C Datasheet, PDF (7/8 Pages) Cherry Semiconductor Corporation – High Performance Dual Channel Current Mode Controller with ENABLE

Operating Description: continued
Design Considerations
High frequency circuit layout techniques are imperative to
prevent pulse-width jitter. This is usually caused by exces-
sive noise pick-up imposed on the current sense and volt-
age feed-back inputs. Noise immunity can be improved by
lowering circuit impedances at these points. The printed
circuit board layout should contain a ground plane with
low current signal and high current switch and output
grounds returning on separate paths back to the input fil-
ter capacitor. Ceramic bypass capacitors (0.1µF) connected
directly to V_CC and V_REF may be required to improve noise
filtering. They provide a low impedance path for filtering
the high frequency noise. All high current loops should be
kept as short as possible using heavy copper runs. The
error amp compensation circuitry and the converter out-
put voltage-divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Timing Diagram
SYNC
C_T
Latch 1
“Set” Input
COMP₁
Sense₁
Latch 1
“Reset” Input
V_OUT1
ENABLE₂
0V
Latch 2
“Set” Input
COMP₂
Sense₂
Latch 2
“Reset” Input
V_OUT2
Applications Diagram
Dual Boost Regulator
V_CC
CF2
V_REF
Sync
5.0V
2.5V
Reference
17V
R
R
Internal
Bias
+
3.4V-
Regulator
+
-
V_REF
UVLO
V_CC ⁺
UVLO -
14V
20kΩ
V_OUT1
R_FB1
R_{T CT}
R_FB2
V_FB1
COMP₁
V_OUT2
ENABLE₂
R_FB3
R_FB4
V_FB2
COMP₂
+
Oscillator
Current Sense
2R ^{Comparator 1}
+
-
Error
1.0mA
Amp 1
+ _0.5V
+
-
R
250µA
PWM
Latch 1
S
R
Q
+
+
-
Error
Amp 2
1.0mA
Current Sense
Comparator 1
2R
0.5V
+
-
R
PWM
Latch 2
S
RQ
R
Gnd Pwr Gnd
7
VIN
CF1 +
L1
D1
Q1
V_OUT1
R_Sense1
L2
D2
Sense₁
Q2
V_OUT2
+
V_OUT1
C_OUT1
+
V_OUT2
C_OUT2
Sense₂
R_Sense2