CS3865C Datasheet, PDF (6/8 Pages) Cherry Semiconductor Corporation – High Performance Dual Channel Current Mode Controller with ENABLE

Operating Description continued
The error amp is compensated externally thru the V_FB and
COMP pins. Its output voltage is offset by two diode
drops (≈1.4V) and divided by three before it connects to
the inverting input of the current sense comparator. This
guarantees that both outputs are disabled when the error
amplifier output is at its lowest state which occurs when
the power supply is operating at light or no-load condi-
tions, or at the beginning of a soft-start interval.
The minimum allowable error amplifier feedback resis-
tance is limited by the amplifier’s source current capability
(0.5 mA) and the output voltage (V_OH) required to reach
the current sense comparator 0.5V clamp level with the
error amplifier inverting input at ground. This condition
happens during initial system start up or when the sensed
output is shorted:
R_F(min)
≈
3
x
0.5V + 1.4V
0.5mA
=
5800Ω
Undervoltage Lockout
Two undervoltage lockout comparators have been incor-
porated to guarantee that the IC is fully functional before
the output stages are enabled. Power supply terminal
(V_CC) and the reference output (V_REF) are monitored by
separate comparator. Each has built-in hysteresis to pre-
vent erratic output behavior as their respective thresholds
are crossed. The upper and lower thresholds of the V_CC
comparator are 14V and 10V respectively.
The V_REF comparator disables the drive outputs until the
internal circuitry is functional. This comparator has upper
and lower thresholds of 3.6V and 3.4V. A 17V zener is con-
nected as a shunt regulator from V_CC to ground to protect
the IC and power MOSFET gate from excessive voltage.
The guaranteed minimum operating voltage after turn-on
is 11V.
Current Sense Comparator and PWM Latch
The CS3865C operates as a current mode controller.
Output switch conduction is initiated by the oscillator and
terminated when the peak inductor current reaches the
threshold level established by the error amplifier output.
Thus the error signal controls the peak inductor current on
a cycle-by-cycle basis. The current sense comparator-PWM
Latch combination ensures that only a single pulse
appears at the drive output (V_OUT) during any given oscil-
lator cycle. The current is converted to a voltage by con-
necting a sense resistor R_Sense in series with the source of
output switch Q1 and ground. This voltage is monitored
through the Sense_1,2 pins and compared to a voltage
derived from the error amp output. The peak current
under normal operating conditions is controlled by the
voltage at COMP where:
I_pk = ^{V(COMP) – 1.4V}
3R_Sense
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage is too
high. Under these conditions, the current sense compara-
tor threshold will be internally clamped to 0.5V. Therefore
the maximum peak switch current is:
I_pk(max)
=
0.5V
R_Sense
Erratic operation due to noise pickup can result if there is
an excessive reduction of the Ipk (max) clamp voltage.
A narrow spike on the leading edge of the current wave-
form can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. The addition of an R_C filter on the current sense
input reduces this spike to an acceptable level.
Outputs and Power Ground
Each channel contains a single totem-pole output stage
that is specifically designed for direct drive of power
MOSFET’s. The outputs have up to ±1.0A peak current
capability and have a typical rise and fall time of 28 ns
with a 1.0nF load. Internal circuitry has been added to
keep the outputs in active pull-down mode whenever an
undervoltage lockout is active, eliminating the need for an
external pull-down resistor.
Although the outputs are optimized for MOSFET’s, they
can easily supply the negative base current required by
bipolar NPN transistors for enhanced turn-off. Since the
outputs do not contain internal current limits an external
series resistor will be required to prevent the peak output
current from exceeding the ±1.0A maximum rating. The
sink saturation (V_OL) is less than 0.4V at 100mA.
A separate ground pin, Pwr Gnd, is provided. Properly
implemented, will significantly reduce the level of switch-
ing transient noise imposed on the control circuitry. This
becomes important when the I_pk(max) clamp level is
reduced.
ENABLE₂
This input is used to switch V_OUT2. V_OUT1 is used to control
circuitry that runs continuously, e.g. volatile memory, the
system clock, or a remote controlled receiver. V_OUT2 out-
put can control the high power circuitry that is turned off
when not needed.
Voltage Reference
The 5.0V bandgap reference is trimmed to ±2.0% toler-
ance. The reference has short circuit protection and is
capable of sourcing 30mA for powering any additional
external circuitry.
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