CS3865C Datasheet, PDF (5/8 Pages) Cherry Semiconductor Corporation – High Performance Dual Channel Current Mode Controller with ENABLE

Typical Performance Characteristics: continued
Reference Voltage Change vs. Source Current
0
V_CC = 15V
-4.0
-8.0
T_A = –55°C
-12
T_A =
-16
25°C
T_A = 125°C
-20
-24
0
20
40
60
80
100 120
I _ref, REFERENCE SOURCE CURRENT (mA)
Reference Short Circuit Current vs. Temperature
120
100
80
60-55
-25 0 25 50 75 100 125
T_A, AMBIENT TEMPERATURE (°C)
Output Saturation Voltage vs. Load Current
0
V_CC
-1.0
-2.0
SOURCE SATURATION
(LOAD TO GROUND)
V_CC=15V
80µS PULSED LOAD
120Hz RATE
T_A=25°C
T_A= –55°C
2.0
1.0
0
0
T_A= –55°C
T_A=25°C
GND
SINK
SATURATION
(LOAD TO V_CC)
200
400
600
800
OUTPUT LOAD CURRENT (mA)
Supply Current vs. Supply Voltage CS3865C
32
R_T=8.2kΩ
CT=3.3nF
24 ^VFB ^1.2=0V
CURRENT SENSE 1.2=0V
T_A=25°C
16
8.0
0
0
4.0
8.0
12
16
20
V_CC, SUPPLY VOLTAGE (V)
Operating Description
The CS3865C is a high performance, fixed frequency, dual
channel current mode PWM controller specifically
designed for off-line and DC to DC converter applications.
It offers the designer a cost effective solution with minimal
external components where independent regulation of two
power converters is required. Each channel contains a high
gain error amplifier, current sensing comparator, pulse
width modulator latch, and totem pole output driver. The
oscillator, reference, and undervoltage lockout circuits are
common to both channels.
Oscillator
The oscillator uses precise frequency and duty cycle con-
trol. The frequency is programmed by the values R_T and
C_T. Capacitor, C_T, is charged and discharged by an equal
magnitude internal current source and sink, generating a
symmetrical 50 percent duty cycle waveform at C_T. The
oscillator peak and valley thresholds are 3.5V and 1.6V
respectively. The source/sink current magnitude is con-
trolled by resistor R_T. For proper operation over tempera-
ture range, its value should be between 4.0kΩ and 16kΩ.
As C_T charges and discharges, an internal blanking pulse
is generated that alternately drives the inputs of the upper
and lower NOR gates high. This, in conjunction with a
precise amount of delay time introduced into each chan-
nel, produces well defined non-overlapping output duty
cycles. The second output, V_OUT2 is enabled while C_T is
charging, and the primary is enabled during the discharge.
Even at 500kHz, each output is capable of approximately
44% duty cycle, making this controller suitable for high
frequency power conversion applications.
In many noise sensitive applications, it may be necessary
to synchronize the converter with an external system
clock. This can be accomplished by applying an external
clock signal. For reliable synchronization, the oscillator fre-
quency should be set about 10% slower than the clock fre-
quency. The rising edge of the clock signal applied to
SYNC, terminates C_T‘s charging and V_OUT2‘s conduction.
By tailoring the clock waveform symmetry, accurate duty
cycle clamping of either output can be achieved.
Error Amplifier
Each channel contains a fully-compensated error amplifi-
er. The output and inverting input nodes are accessible.
The amplifier features a typical dc voltage gain of 100 dB,
and a unity gain bandwidth of 1.0 MHz with 71 degrees of
phase margin. The non-inverting input is internally biased
at 2.5V. The converter output voltage is typically divided
down and monitored by the inverting input through a
resistor divider. The maximum input bias current is -1.0µA
which will cause an output voltage error that is equal to
the product of the input bias current and the equivalent
input divider resistance.
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