CM6802A_12 Datasheet, PDF (20/25 Pages) Champion Microelectronic Corp. – EPA/80++ ZVS-Like PFC/PWM COMBO CONTROLLER

CM6802A/B/AH/BH (Dynamic Soft PFC/Green PWM)
http://www.championmicro.com.tw EPA/80++ ZVS-Like PFC/PWM COMBO CONTROLLER
Design for High Efficient Power Supply at both Full Load and Light Load
PWM Control (RAMP2)
When the PWM section is used in current mode, RAMP2 is
generally used as the sampling point for a voltage
representing the current on the primary of the PWM’s output
transformer, derived either by a current sensing resistor or a
current transformer. In voltage mode, it is the input for a ramp
voltage generated by a second set of timing components
(R_RAMP2, C_RAMP2),that will have a minimum value of zero volts
and should have a peak value of approximately 5V. In voltage
mode operation, feed-forward from the PFC output buss is an
excellent way to derive the timing ramp for the PWM stage.
Soft Start (SS)
Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 10 μ A supplies
the charging current for the capacitor, and start-up of the
PWM begins at SS~1.4V. Start-up delay can be programmed
by the following equation:
C_SS = t_DELAY x ^10μA
1.8V
where C_SS is the required soft start capacitance, and the t_DEALY
is the desired start-up delay.
It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for the
PWM section. The PWM start-up delay should be at least
5ms.
Solving for the minimum value of C_SS:
C_SS = 5ms x ^10μA ≒ 27nF
1.8V
Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the
SS capacitor and activation of the PWM section can result if
VFB is in the hysteresis band of the 380V-OK comparator at
start-up. The magnitude of V_FB at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a
0.05 μ F soft start capacitor will allow time for V_FB and PFC
out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and 265Vrms.
Generating V_CC
After turning on CM6802A/B/AH/BH at 13V, the operating
voltage can vary from 10V to 17.9V. That’s the two ways to
generate VCC. One way is to use auxiliary power supply
around 15V, and the other way is to use bootstrap winding to
self-bias CM6802A/B/AH/BH system. The bootstrap winding
can be either taped from PFC boost choke or from the
transformer of the DC to DC stage. The ratio of winding
transformer for the bootstrap should be set between 18V and
15V.
A filter network is recommended between VCC (pin 13) and
bootstrap winding. The resistor of the filter can be set as
following.
R_FILTER x I_VCC ~ 2V, I_VCC = I_OP + (Q_PFCFET + Q_PWMFET ) x fsw
I_OP = 3mA (typ.)
If anything goes wrong, and VCC goes beyond 19.4V, the
PFC gate (pin 12) drive goes low and the PWM gate drive (pin
11) remains function. The resistor’s value must be chosen to
meet the operating current requirement of the
CM6802A/B/AH/BH itself (5mA, max.) plus the current required
by the two gate driver outputs.
EXAMPLE:
With a wanting voltage called, V_BIAS ,of 18V, a VCC of 15V
and the CM6802A/B/AH/BH driving a total gate charge of 90nC
at 100kHz (e.g. 1 IRF840 MOSFET and 2 IRF820 MOSFET),
the gate driver current required is:
I_GATEDRIVE = 100kHz x 90nC = 9mA
R_BIAS = ^{VBIAS − VCC}
ICC + IG
R_BIAS = ^{18V − 15V}
5mA + 9mA
Choose R_BIAS = 214Ω
The CM6802A/B/AH/BH should be locally bypassed with a
1.0 μ F ceramic capacitor. In most applications, an electrolytic
capacitor of between 47 μ F and 220 μ F is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn on
right after the trailing edge of the system clock. The error
amplifier output is then compared with the modulating ramp up.
The effective duty cycle of the trailing edge modulation is
determined during the ON time of the switch. Figure 4 shows a
typical trailing edge control scheme.
2012/05/10 Rev. 1.5
Champion Microelectronic Corporation
20