CM6802A_12 Datasheet, PDF (14/25 Pages) Champion Microelectronic Corp. – EPA/80++ ZVS-Like PFC/PWM COMBO CONTROLLER

CM6802A/B/AH/BH (Dynamic Soft PFC/Green PWM)
http://www.championmicro.com.tw EPA/80++ ZVS-Like PFC/PWM COMBO CONTROLLER
Design for High Efficient Power Supply at both Full Load and Light Load
Getting Start:
Power Factor Correction
To start evaluating CM6802A/B/AH/BH from the exiting
CM6800 or ML4800 board, 6 things need to be taken care
before doing the fine tune:
1.) Change RAC resistor (on pin 2, IAC) from the old value
to a higher resistor value between 4.7 Mega ohms to 8
Mega ohms.
2.) Change RTCT pin (pin 7) from the existing value to
RT=7.0K ohm and CT=1000pF to have fpfc=55 Khz,
fpwm=55Khz, fRTCT=220Khz for CM6802A/AH and
fpfc=55 Khz, fpwm=110Khz, fRTCT=220Khz for
CM6802B/BH.
3.) Adjust all high voltage resistor around 5 mega ohm or
higher.
4.) VRMS pin (pin 4) needs to be 1.125V at VIN=85VAC for
universal input application from line input from 85VAC to
270VAC. Both poles for the Vrms of the
CM6802A/B/AH/BH needs to substantially slow than
CM6800 about 5 to 10 times.
5.) At full load, the average Veao needs to around 4.5V and
the ripple on the Veao needs to be less than 250mV.
6.) Soft Start pin (pin 5), the soft start current has been
reduced from CM6800’s 20uA to CM6802A/B/AH/BH’s
10uA.Soft Start capacitor can be reduced to 1/2 from your
original CM6800 capacitor.
Functional Description
CM6802A/B/AH/BH is designed for high efficient power
supply for both full load and light load. It is a popular
EPA/80++ PFC-PWM power supply controller.
The CM6802A/B/AH/BH consists of an average current
controlled, continuous/discontinuous boost Power Factor
Correction (PFC) front end and a synchronized Pulse Width
Modulator (PWM) back end. The PWM can be used in either
current or voltage mode. In voltage mode, feed-forward from
the PFC output bus can be used to improve the PWM’s line
regulation. In either mode, the PWM stage uses conventional
trailing edge duty cycle modulation, while the PFC uses
leading edge modulation. This patented leading/trailing edge
modulation technique results in a higher usable PFC error
amplifier bandwidth, and can significantly reduce the size of
the PFC DC buss capacitor.
The synchronized of the PWM with the PFC simplifies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor).
In addition to power factor correction, a number of
protection features have been built into the
CM6802A/B/AH/BH. These include soft-start, PFC
over-voltage protection, peak current limiting, brownout
protection, duty cycle limiting, and under-voltage lockout.
Power factor correction makes a nonlinear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with and proportional to the line voltage,
so the power factor is unity (one). A common class of nonlinear
load is the input of most power supplies, which use a bridge
rectifier and capacitive input filter fed from the line. The
peak-charging effect, which occurs on the input filter capacitor in
these supplies, causes brief high-amplitude pulses of current to
flow from the power line, rather than a sinusoidal current in
phase with the line voltage. Such supplies present a power
factor to the line of less than one (i.e. they cause significant
current harmonics of the power line frequency to appear at their
input). If the input current drawn by such a supply (or any other
nonlinear load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC line
and a unity power factor will be achieved.
To hold the input current draw of a device drawing power from
the AC line in phase with and proportional to the input voltage, a
way must be found to prevent that device from loading the line
except in proportion to the instantaneous line voltage. The PFC
section of the CM6802A/B/AH/BH uses a boost-mode DC-DC
converter to accomplish this. The input to the converter is the full
wave rectified AC line voltage. No bulk filtering is applied
following the bridge rectifier, so the input voltage to the boost
converter ranges (at twice line frequency) from zero volts to the
peak value of the AC input and back to zero. By forcing the
boost converter to meet two simultaneous conditions, it is
possible to ensure that the current drawn from the power line is
proportional to the input line voltage. One of these conditions is
that the output voltage of the boost converter must be set higher
than the peak value of the line voltage. A commonly used value
is 385VDC, to allow for a high line of 270VAC_rms. The other
condition is that the current drawn from the line at any given
instant must be proportional to the line voltage. Establishing a
suitable voltage control loop for the converter, which in turn
drives a current error amplifier and switching output driver
satisfies the first of these requirements. The second requirement
is met by using the rectified AC line voltage to modulate the
output of the voltage control loop. Such modulation causes the
current error amplifier to command a power stage current that
varies directly with the input voltage. In order to prevent ripple,
which will necessarily appear at the output of boost circuit
(typically about 10VAC on a 385V DC level); from introducing
distortion back through the voltage error amplifier, the bandwidth
of the voltage loop is deliberately kept low. A final refinement is
to adjust the overall gain of the PFC such to be proportional to
1/(Vin x Vin), which linearizes the transfer function of the system
as the AC input to voltage varies.
Since the boost converter topology in the CM6802A/B/AH/BH
PFC is of the current-averaging type, no slope compensation is
required.
More exactly, the output current of the gain modulator is given
by:
2012/05/10 Rev. 1.5
Champion Microelectronic Corporation
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