THC63LVD1023B Datasheet, PDF (10/26 Pages) THine Electronics, Inc. – 160MHz 67Bits LVDS Transmitter

AC Timing Diagrams
V_diff=(TA+)-(TA-)
80%
TA+
V_diff
5pF _100Ω
20%
TA-
LVDS Output Load
t_LVT
Fig2. LVDS Output Load and Transition Time
80%
20%
t_LVT
CLKINx
x=1,2
/PDWN
2.0V
TCLKx+/-
x=1,2
t_TPLL
Fig3. PLL Lock Time
V_diff=0V
CLKIN
t_TCIP
t_DEINT
DE
t_DEH
t_DEL
Note: In single-in/dual-out, DDR off mode (MODE<2:0>=LHL),
the period between rising edges of DE (t_DEINT), high time of DE (t_DEH)
should always satisfy following equations.
t_DEH = tTCIP * (2m)
t_DEINT = tTCIP * (2n)
m, n =integer
Fig3-1. Single IN / Dual OUT, DDR off mode DE input timing
THC63LVD1023B_Rev.3.0_E
Copyright©2011 THine Electronics, Inc.
10/26
THine Electronics, Inc.