THC63LVD1023B Datasheet, PDF (1/26 Pages) THine Electronics, Inc. – 160MHz 67Bits LVDS Transmitter

THC63LVD1023B
160MHz 67Bits LVDS Transmitter
General Description
The THC63LVD1023B transmitter is designed to suport
Single Link transmission between Host and Flat Panel
Display up to 1080p(60Hz) resolutions and Dual Link
transmission between Host and Flat Panel Display up to
1080p(120Hz).
The THC63LVD1023B converts 67bits of CMOS/TTL
data into LVDS (Low Voltage Differential Signaling)
data stream. The transmitter can be programmed for ris-
ing edge or falling edge clocks through a dedicated pin,
and support double edge inputs.
In Dual Link, the transmit clock frequency of 160MHz,
67bits of RGB data are transmitted at an effective rate
of 1.12Gbps per LVDS channel.
In Asynchronous mode, the THC63LVD1023B has 2
independent 35Bits Transmitter.
Block Diagram
Features
• Wide dot clock range suited for TV Signal (480i-
1080p), PC Signal (VGA-QXGA)
TTL/CMOS Input: 10-160MHz
LVDS Output: 20-160MHz
• PLL requires No external components
• Flexible Input/Output mode
1. Single/Dual TTL IN, Single/Dual LVDS OUT
2. Double edge input for Single TTL IN/Dual LVDS OUT
3. Input port SW for Single TTL IN/Dual LVDS OUT
4. Asynchronous Dual TTL IN/Dual LVDS OUT
• Clock edge selectable
• 3 LVDS data mapping for simplifying PCB layout.
• Pseudo Random pattern generation circuit
• Supports Reduced swing LVDS for Low EMI
• Power down mode
• Low power single 3.3V CMOS design
• Backward compatible with THC63LVD1023
• 144pin LQFP
R1[9:0]
DATA Port1
G1[9:0]
B1[9:0]
32
CONT1[2:1]
DATA Port2
R2[9:0]
G2[9:0] ₃₂
B2[9:0]
CONT2[2:1]
Hsync1
Vsync1
DE1
6
Hsync2
Vsync2
DE2
R/F
RS
MAP
MODE[3:0]
/PDWN
PRBS
ASYNC
CLKIN1
CLKIN2
TRANSMITTER CLOCK IN
(10 to 160MHz)
THC63LVD1023B_Rev.3.0_E
Copyright©2011 THine Electronics, Inc.
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35
MUX PLL
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TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TE1 +/-
LVDS OUTPUT
Port1
TA2 +/-
TB2 +/-
TC2 +/-
TD2 +/-
TE2 +/-
LVDS OUTPUT
Port2
TCLK1 +/-
TCLK2 +/-
(20 to 160MHz)
THine Electronics, Inc.