CAT93C56_07 Datasheet, PDF (9/18 Pages) Catalyst Semiconductor – 2-Kb Microwire Serial CMOS EEPROM

CAT93C56, CAT93C57
Erase All
Upon receiving an ERAL command (Figure 6), the CS
(Chip Select) pin must be deselected for a minimum of
t_CSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the
device has entered the self clocking mode. The
ready/busy status of the CAT93C56/57 can be deter-
mined by selecting the device and polling the DO pin.
Once cleared, the contents of all memory bits return to
a logical “1” state.
Write All
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
t_CSMIN (Figure 7). The falling edge of CS will start the
self clocking data write to all memory locations in the
device. The clocking of the SK pin is not necessary
after the device has entered the self clocking mode.
The ready/busy status of the CAT93C56/57 can be
determined by selecting the device and polling the DO
pin. It is not necessary for all memory locations to be
cleared before the WRAL command is executed.
Figure 6. ERAL Instruction Timing
SK
CS
DI
1
00
10
HIGH-Z
DO
Figure 7. WRAL Instruction Timing
SK
STATUS VERIFY
tCS
STANDBY
tSV
BUSY
tEW
READY
tHZ
HIGH-Z
CS
DI
1
000
1
DO
STATUS VERIFY STANDBY
tCSMIN
DN
D0
tSV
tHZ
BUSY
tEW
READY
HIGH-Z
© Catalyst Semiconductor, Inc.
9
Characteristics subject to change without notice
Doc. No. MD-1088 Rev. P