CAT93C56_07 Datasheet, PDF (4/18 Pages) Catalyst Semiconductor – 2-Kb Microwire Serial CMOS EEPROM

CAT93C56, CAT93C57
A.C. CHARACTERISTICS⁽¹⁾, CAT93C56, Die Rev. G – New Product
V_CC = +1.8V to +5.5V, T_A = -40°C to +85°C, unless otherwise specified.
Symbol
t_CSS
t_CSH
t_DIS
t_DIH
t_PD1
t_PD0
t_HZ(2)
t_EW
t_CSMIN
t_SKHI
t_SKLOW
t_SV
SK_MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
Limits
Min
50
0
100
100
0.25
0.25
0.25
DC
Max
0.25
0.25
100
5
0.25
2000
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
A.C. CHARACTERISTICS ⁽¹⁾, CAT93C56/57, Die Rev. E – Mature Product
(CAT93C56 Rev. E - NOT RECOMMENDED FOR NEW DESIGNS)
Limits
Symbol Parameter
V_CC = 1.8V - 5.5V
Min
Max
V_CC = 2.5V - 5.5V
Min
Max
t_CSS CS Setup Time
200
t_CSH CS Hold Time
0
t_DIS DI Setup Time
400
t_DIH DI Hold Time
400
t_PD1 Output Delay to 1
1
t_PD0 Output Delay to 0
1
t_HZ(2) Output Delay to High-Z
400
t_EW Program/Erase Pulse Width
10
t_CSMIN Minimum CS Low Time
1
t_SKHI Minimum SK High Time
1
t_SKLOW Minimum SK Low Time
1
t_SV Output Delay to Status Valid
1
SK_MAX Maximum Clock Frequency
DC
250
100
0
200
200
0.5
0.5
200
10
0.5
0.5
0.5
0.5
DC
500
V_CC = 4.5V - 5.5V
Min
Max
50
0
100
100
0.25
0.25
100
10
0.25
0.25
0.25
0.25
DC
1000
Units
ns
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
kHz
Notes:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC-Q100 and JEDEC test methods.
Doc. No. MD-1088 Rev. P
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice