CAT34RC02 Datasheet, PDF (8/16 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34RC02
by the CAT34RC02, then the device will continue
transmitting as long as each data byte is acknowledged
by the Master (Fig. 13). If the end of memory is reached
during sequential READ, the address counter will ‘wrap-
around’ to the beginning of memory, etc. Sequential
READ works with either ‘Immediate Address Read’ or
‘Selective Read’, the only difference being the starting
byte address.
Figure 9. Memory Array
FFH
Hardware Write Protectable
(by connecting WP pin to
7FH
Vcc)
Software Write Protectable
(by setting the write
protect flags)
00H
Figure 10. Software Write Protect (Write)
S
T
BUS ACTIVITY: ^A
MASTER ^R
T
SDA LINE S
SLAVE
ADDRESS
BYTE
ADDRESS
S
T
DATA
O
P
XXXXXXXX XXXXXXXX P
A
A
A
C
C
C
K
K
K
X = Don't Care
* For PSWP A₀ is at normal CMOS levels and for RSWP, A₀ is at V_HV which must be held high beyond the end
of the STOP condition (approximately 1µs of “overlap” is sufficient).
Doc. No. 1052, Rev. I
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