CAT34RC02 Datasheet, PDF (7/16 Pages) Catalyst Semiconductor – 2-kb I2C Serial EEPROM, Serial Presence Detect

CAT34RC02
The PSWP flag can be set (forever) by issuing a ‘Byte
Write’ command, with the Slave address preamble set to
‘6h’, followed by a ‘don’t care’ address, followed by ‘don’t
care’ data and a STOP condition. The CAT34RC02 will
acknowledge the Slave address, dummy byte address
and dummy data (Fig. 10). The PSWP flag will be
permanently set (after the internal write cycle is
completed).
The SWP commands are shown in Table 1.
Table 1. SWP Commands
Slave Address
Command
SWP
READ
RSWP SET
RSWP
CLEAR
PSWP SET
PIN
A2 A1 A0
Preamble
Device Address R/W
B7 B6 B5 B4 B3 B2 B1 B0
A2 A1 A0 0
1 1 0 A2 A1 A0
1
0 0 VHV 0
1 10
0
0
1
0
0
1 VHV 0
1 10
0
11
0
A2 A1 A0 0
1 1 0 A2 A1 A0
0
The CAT34RC02 will not acknowledge RSWP or PSWP
commands, once the PSWP flag is set. If the PSWP flag
is not set, but the WP pin is HIGH, then the CAT34RC02
will react to RSWP or PSWP commands as follows: if the
command attempts to ‘flip’ one of the two SWP switches,
then the CAT34RC02 will respond the same way the
regular memory would, i.e. the command and address
(in this case dummy) are acknowledged, but the data (in
this case dummy) will not be acknowledged; if the
command attempts to ‘reaffirm’ one of the two switches,
then the CAT34RC02 will not acknowledge the command
itself. In addition, the CAT34RC02 will not acknowledge
a ‘reaffirming’ SWP command, even if the WP pin is
LOW.
READ OPERATIONS
Immediate Address Read
In standby mode, the CAT34RC02 internal address
counter points to the data byte immediately following the
last byte accessed by a previous operation. If the
‘previous’ byte was the last byte in memory, then the
address counter will point to the first memory byte, etc.
If the CAT34RC02 decodes a Slave address with a ‘1’ in
the R/W bit position (Fig. 8), it will issue an ACK in the 9^th
clock cycle, and will then transmit the data byte being
pointed at by the address counter. The Master can then
stop further transmission by issuing a NoACK, followed
by a STOP condition.
Selective Read
The READ operation can also be started at an address
different from the one stored in the address counter. The
address counter can be ‘initialized’ by performing a
‘dummy’ WRITE operation (Fig. 12). The START
condition is followed by the Slave address (with the R/W
bit set to ‘0’) and the desired byte address. Instead of
following up with data, the Master then issues a 2^nd
START, followed by the ‘Immediate Address Read’
sequence, as described earlier.
Sequential Read
If the Master acknowledges the 1^st data byte transmitted
Figure 8. Immediate Address Read Timing
S
T
S
BUS ACTIVITY: ^A
SLAVE
T
MASTER ^R ADDRESS
O
T
P
SDA LINE S
P
A
N
C
DATA
O
K
A
C
K
SCL
8
9
SDA
8th Bit
DATA OUT
NO ACK
STOP
7
Doc No. 1052, Rev. I