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CAT35C804A Datasheet, PDF (7/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM | |||
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Preliminary
CAT35C804A
also go to the high impedance state if an error condition
is detected. In the event an ENABLE BUSY instruction
has not been sent, a READ STATUS register instruction
can be executed. This also tells the user whether the part
is in a program/erase cycle or an error condtion. When
the device is in a program/erase cycle it will output an
8-bit status word. If it does not, it is in an error condition.
PE
The Parity Enable pin is a TTL compatible input. If the PE
pin is set HIGH, the device will be configured to commu-
nicate using even parity, and if the pin is set LOW, it will
use no parity. In this case, instructions or data that
include parity bits will not be interpreted correctly. Note:
The PE input is internally pulled down to GND (i.e.
default = no parity). As with all CMOS devices, CS, CLK
and DI inputs must be connected to either HIGH or LOW,
and not left floating.
ERR
The Error indication pin is an open drain output. If either
an instruction or parity error exists, the ERR pin will
output a â0â until the device is reset. This can be done by
pulsing CS LOW.
Figure 6. Read Timing (x8 Format)
VCC
CLK
CS
OP CODE
ADDRESS
OP0âOP7
A8âA15
DI
DO
HIGH-Z
Figure 7. Read Timing (x16 Format)
VCC
ADDRESS
A0âA7
DATA
D0âD7
35C804 F09
CLK
CS
OP CODE
ADDRESS
OP0âOP7
A0âA7
DI
DATA
DATA
DO
HIGH-Z
D8âD15
D0âD7
HIGH-Z
35C804 F10
7
Doc. No. 25043-00 2/98
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