CAT35C804A Datasheet, PDF (10/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM

CAT35C804A
Preliminary
As shipped from the factory, the device is in the unpro-
tected mode. The length of the access code is user
selectable from a minimum of one byte to a maximum of
eight bytes (> 1.84x10¹⁹ combinations). Loading a zero-
length access code will disable protection.
MEMORY POINTER REGISTER
The memory pointer enables the user to segment the
E²PROM array into two sections. In the unprotected
mode, the array can be segmented between read-only
and full access, while in the secure mode, the memory
may be segmented between read-only access and
password-only access. Three instructions are dedicated
to the memory pointer operations. The first one is WMPR
(Write Memory Pointer Register). This instruction, fol-
lowed by an address, will load the memory pointer
register with a new address. This address will be stored
in the E²PROM and can be modified only by another
WMPR instruction. The second instruction is OVMPR
(Override Memory Pointer Register) which allows a
single program/erase to be performed to memory loca-
tions below the address set in the memory pointer. This
instruction allows the user to modify data in a segmented
array without having to move the memory pointer. Once
the operation is complete, the device returns to the
protected mode. If the device is in the secure mode both
of these instructions require the ENAC instruction and a
valid access code prior to their execution. The third
instruction is the RMPR (Read Memory Pointer Regis-
ter) which will place the current contents of the register
in the serial output buffer.
STATUS REGISTER
An eight bit status register is provided to allow the user
to determine the status of the CAT35C804A. The con-
tents of the first three bits of the register are 101 which
allows the user to quickly determine the condition of the
device. The next three bits indicate the status of the
device; they are parity error, instruction error and RDY/
BUSY status. The last two bits are reserved for future
use.
CLEAR ALL AND WRITE ALL
As a precaution, the ERAL instruction has to be entered
twice before it is executed. This measure is required as
a redundancy check on the incoming instruction for
possible transmission errors. The WRAL instruction
requires sending an ERAL first (this sets a flag only) and
Figure 11. Erase Timing (x8 Format)
CS
OP CODE
ADDRESS
OP0–OP7
A8–A15
DI
ADDRESS
A0–A7
DO
HIGH-Z
tEW
BUSY(1)
NEXT INSTRUCTION
35C804 F12
Figure 12. Erase Timing (x16 Format)
CS
OP CODE
ADDRESS
OP0–OP7
A0–A7
DI
NEXT INSTRUCTION
tEW
DO
HIGH-Z
BUSY(1)
35C804 F13
Note:
(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in High-Z
condition.
Doc. No. 25043-00 2/98
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