CAT35C804A Datasheet, PDF (12/14 Pages) Catalyst Semiconductor – 4K-Bit Secure Access Serial E2PROM

CAT35C804A
Preliminary
INSTRUCTION SET
DISAC Disable Access
1000 1000
This instruction will lock the memory from all program/
erase operations regardless of the contents of the memory
pointer. A write can be accomplished only by first enter-
ing the ENAC instruction followed by a valid access
code.
ENAC Enable Access
1100 0101 [Access Code]
In the protected mode, this instruction, followed by a
valid access code, unlocks the device for read/write/
clear access.
WMPR Write Memory Pointer Register
1100 0100 [A15–A8] [A7–A0] (x8 organization)
1100 0100 [A7–A0] (x16 organization)
The WMPR instruction followed by 8 or 16 bits of
address (depending on the organization) will move the
pointer to the newly specified address.
MACC Modify Access Code
1101 [Length] [Old code] [New code]
[New code]
This instruction requires the user to enter the old access
code, if one was set previously, followed by the new
access code and a re-entry of the new access code for
verification. Within the instruction format, the variable
[Length] designates the length of the access code as the
following:
[Length] = [0] No access code. Set device to unpro-
tected mode.
[Length] = [1–8] Length of access code is 1 to 8 bytes.
[Length] = [>8] Illegal number of bytes. The CAT35C804A
will ignore the rest of the transmission.
RMPR Read Memory Pointer Register
1100 1010
Output the content of the memory pointer register to the
serial output port.
Figure 14. ERAL Timing (x8 Format)
CS
OP CODE
OP CODE
OP0–OP7
OP0–OP7
DI
DO
HIGH-Z
tEW
BUSY(1)
NEXT INSTRUCTION
35C804 F15
Figure 15. ERAL Timing (x16 Format)
CS
OP CODE
OP CODE
OP0–OP7
OP0–OP7
DI
DO
HIGH-Z
tEW
BUSY(1)
NEXT INSTRUCTION
35C804 F16
Note:
(1) DO becomes low to indicate busy status if ENBSY was previously executed. If ENBSY was not previously executed, DO will be in the
High-Z condition.
Doc. No. 25043-00 2/98
12