CAT28C512_04 Datasheet, PDF (7/12 Pages) Catalyst Semiconductor – 512K-Bit CMOS PARALLEL EEPROM

CAT28C512/513
Page Write
The page write mode of the CAT28C512/513 (essen-
tially an extended BYTE WRITE mode) allows from 1 to
128 bytes of data to be programmed within a single
EEPROM write cycle. This effectively reduces the byte-
write time by a factor of 128.
Following an initial WRITE operation (WE pulsed low, for
t_WP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
and data bytes into a 128 byte temporary buffer. The
page address where data is to be written, specified by
bits A₇ to A₁₅, is latched on the last falling edge of WE.
Each byte within the page is defined by address bits A₀
to A₆ (which can be loaded in any order) during the first
and subsequent write cycles. Each successive byte load
cycle must begin within t_{BLC MAX} of the rising edge of the
preceding WE pulse. There is no page write window
limitation as long as WE is pulsed low within t_{BLC MAX}.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
which writes new data back into the cell. A page write will
only write data to the locations that were addressed and
will not rewrite the entire page.
Figure 5. Byte Write Cycle [CE Controlled]
tWC
ADDRESS
tAS
CE
tAH
tCW
tBLC
tOEH
OE
tOES
tCS
tCH
WE
DATA OUT
HIGH-Z
DATA IN
DATA VALID
tDS
tDH
Figure 6. Page Mode Write Cycle
OE
CE
tWP
tBLC
WE
ADDRESS
I/O
BYTE 0 BYTE 1
BYTE 2
BYTE n BYTE n+1
tWC
LAST BYTE
BYTE n+2
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Doc. No. 1007, Rev . E