CAT24FC01_05 Datasheet, PDF (7/10 Pages) Catalyst Semiconductor – 1-kb I2C Serial EEPROM

CAT24FC01
Read Operations
The READ operation for the CAT24FC01 is initiated in
the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
read. After the CAT24FC01 acknowledge the word
address, the Master device resends the START condition
and the slave address, this time with the R/W bit set to
one. The CAT24FC01 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
Immediate Address Read
Sequential Read
The CAT24FC01’s address counter contains the address _{The Sequential READ operation can be initiated by}
of the last byte accessed, incremented by one. In other
words, if the last READ or WRITE access was to
address N, the READ immediately following would
access data from address N + 1. If N = 217, the counter
t _{will not ‘wrap around’. After the CAT24FC01 receives its}
r ^{slave address information (with the R/W bit set to one),}
it issues an acknowledge, then transmits the 8-bit byte
a ^{requested. The master device does not send an}
acknowledge but will generate a STOP condition.
P ^{Selective Read}
Selective READ operations allow the Master device to
select at random any memory location for a READ
d ^{operation. The Master device first performs a ‘dummy’}
write operation by sending the START condition, slave
address and byte address of the location it wishes to
either the Immediate Address READ or Selective READ
operations. After the CAT24FC01 sends the initial 8-bit
data requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24FC01 will continue to output a byte for
each acknowledge sent by the Master. The operation
will terminate operation when the Master fails to respond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from the CAT24FC01 is
outputted sequentially with data from address N followed
by data from address N + 1. The READ operation
address counter increments all of the CAT24FC01
address bits so that the entire memory array can be
read during one operation.
ue _{Figure 8. Immediate Address Read Timing}
tin ^S
T
S
BUS ACTIVITY: ^A
SLAVE
T
MASTER ^R ADDRESS
O
T
P
n_{SDA LINE S}
P
o_A
N
C
DATA
O
K
cA
C
K
Dis^SCL
8
9
SDA
8TH BIT
DATA OUT
NO ACK
STOP
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. 1073, Rev. G